+ { 188, 188, 1 << 3, ANYMUX, V3D_QPU_A_RSQRT, 41 },
+ { 188, 188, 1 << 4, ANYMUX, V3D_QPU_A_EXP, 41 },
+ { 188, 188, 1 << 5, ANYMUX, V3D_QPU_A_LOG, 41 },
+ { 188, 188, 1 << 6, ANYMUX, V3D_QPU_A_SIN, 41 },
+ { 188, 188, 1 << 7, ANYMUX, V3D_QPU_A_RSQRT2, 41 },