- RegIndex idx = inst->destRegIdx(start_idx);
- if (idx < TheISA::FP_Base_DepTag) {
- thread->setIntReg(idx, mismatch_val);
- } else if (idx < TheISA::Ctrl_Base_DepTag) {
- thread->setFloatRegBits(idx, mismatch_val);
- } else if (idx < TheISA::Max_DepTag) {
- thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
- mismatch_val);
+ const RegId& idx = inst->destRegIdx(start_idx);
+ switch (idx.classValue()) {
+ case IntRegClass:
+ panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
+ thread->setIntReg(idx.index(), mismatch_val.asInteger());
+ break;
+ case FloatRegClass:
+ panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
+ thread->setFloatReg(idx.index(), mismatch_val.asInteger());
+ break;
+ case VecRegClass:
+ panic_if(!mismatch_val.isVector(), "Unexpected type of result");
+ thread->setVecReg(idx, mismatch_val.asVector());
+ break;
+ case VecElemClass:
+ panic_if(!mismatch_val.isVecElem(),
+ "Unexpected type of result");
+ thread->setVecElem(idx, mismatch_val.asVectorElem());
+ break;
+ case CCRegClass:
+ panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
+ thread->setCCReg(idx.index(), mismatch_val.asInteger());
+ break;
+ case MiscRegClass:
+ panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
+ thread->setMiscReg(idx.index(), mismatch_val.asInteger());
+ break;
+ default:
+ panic("Unknown register class: %d", (int)idx.classValue());