+ virtual void setFloatRegOperandBits(const StaticInst *si,
+ int idx, RegVal val) = 0;
+
+ /** @} */
+
+ /** Vector Register Interfaces. */
+ /** @{ */
+ /** Reads source vector register operand. */
+ virtual const VecRegContainer&
+ readVecRegOperand(const StaticInst *si, int idx) const = 0;
+
+ /** Gets destination vector register operand for modification. */
+ virtual VecRegContainer&
+ getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
+
+ /** Sets a destination vector register operand to a value. */
+ virtual void
+ setVecRegOperand(const StaticInst *si, int idx,
+ const VecRegContainer& val) = 0;
+ /** @} */
+
+ /** Vector Register Lane Interfaces. */
+ /** @{ */
+ /** Reads source vector 8bit operand. */
+ virtual ConstVecLane8
+ readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
+
+ /** Reads source vector 16bit operand. */
+ virtual ConstVecLane16
+ readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
+
+ /** Reads source vector 32bit operand. */
+ virtual ConstVecLane32
+ readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
+
+ /** Reads source vector 64bit operand. */
+ virtual ConstVecLane64
+ readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
+
+ /** Write a lane of the destination vector operand. */
+ /** @{ */
+ virtual void setVecLaneOperand(const StaticInst *si, int idx,
+ const LaneData<LaneSize::Byte>& val) = 0;
+ virtual void setVecLaneOperand(const StaticInst *si, int idx,
+ const LaneData<LaneSize::TwoByte>& val) = 0;
+ virtual void setVecLaneOperand(const StaticInst *si, int idx,
+ const LaneData<LaneSize::FourByte>& val) = 0;
+ virtual void setVecLaneOperand(const StaticInst *si, int idx,
+ const LaneData<LaneSize::EightByte>& val) = 0;
+ /** @} */
+
+ /** Vector Elem Interfaces. */
+ /** @{ */
+ /** Reads an element of a vector register. */
+ virtual VecElem readVecElemOperand(const StaticInst *si,
+ int idx) const = 0;
+
+ /** Sets a vector register to a value. */
+ virtual void setVecElemOperand(const StaticInst *si, int idx,
+ const VecElem val) = 0;
+ /** @} */
+
+ /** Predicate registers interface. */
+ /** @{ */
+ /** Reads source predicate register operand. */
+ virtual const VecPredRegContainer&
+ readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
+
+ /** Gets destination predicate register operand for modification. */
+ virtual VecPredRegContainer&
+ getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
+
+ /** Sets a destination predicate register operand to a value. */
+ virtual void
+ setVecPredRegOperand(const StaticInst *si, int idx,
+ const VecPredRegContainer& val) = 0;
+ /** @} */
+
+ /**
+ * @{
+ * @name Condition Code Registers
+ */
+ virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
+ virtual void setCCRegOperand(
+ const StaticInst *si, int idx, RegVal val) = 0;
+ /** @} */
+
+ /**
+ * @{
+ * @name Misc Register Interfaces
+ */
+ virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
+ virtual void setMiscRegOperand(const StaticInst *si,
+ int idx, RegVal val) = 0;
+
+ /**
+ * Reads a miscellaneous register, handling any architectural
+ * side effects due to reading that register.
+ */
+ virtual RegVal readMiscReg(int misc_reg) = 0;
+
+ /**
+ * Sets a miscellaneous register, handling any architectural
+ * side effects due to writing that register.
+ */
+ virtual void setMiscReg(int misc_reg, RegVal val) = 0;
+
+ /** @} */
+
+ /**
+ * @{
+ * @name PC Control
+ */
+ virtual PCState pcState() const = 0;
+ virtual void pcState(const PCState &val) = 0;
+ /** @} */
+
+ /**
+ * @{
+ * @name Memory Interface
+ */
+ /**
+ * Perform an atomic memory read operation. Must be overridden
+ * for exec contexts that support atomic memory mode. Not pure
+ * virtual since exec contexts that only support timing memory
+ * mode need not override (though in that case this function
+ * should never be called).
+ */
+ virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
+ Request::Flags flags,
+ const std::vector<bool>& byteEnable = std::vector<bool>())
+ {
+ panic("ExecContext::readMem() should be overridden\n");
+ }
+
+ /**
+ * Initiate a timing memory read operation. Must be overridden
+ * for exec contexts that support timing memory mode. Not pure
+ * virtual since exec contexts that only support atomic memory
+ * mode need not override (though in that case this function
+ * should never be called).
+ */
+ virtual Fault initiateMemRead(Addr addr, unsigned int size,
+ Request::Flags flags,
+ const std::vector<bool>& byteEnable = std::vector<bool>())
+ {
+ panic("ExecContext::initiateMemRead() should be overridden\n");
+ }
+
+ /**
+ * For atomic-mode contexts, perform an atomic memory write operation.
+ * For timing-mode contexts, initiate a timing memory write operation.
+ */
+ virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
+ Request::Flags flags, uint64_t *res,
+ const std::vector<bool>& byteEnable =
+ std::vector<bool>()) = 0;
+
+ /**
+ * For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic
+ * Read-Modify-Write Memory Operation)
+ */
+ virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
+ Request::Flags flags,
+ AtomicOpFunctorPtr amo_op)
+ {
+ panic("ExecContext::amoMem() should be overridden\n");
+ }
+
+ /**
+ * For timing-mode contexts, initiate an atomic AMO (atomic
+ * read-modify-write memory operation)
+ */
+ virtual Fault initiateMemAMO(Addr addr, unsigned int size,
+ Request::Flags flags,
+ AtomicOpFunctorPtr amo_op)
+ {
+ panic("ExecContext::initiateMemAMO() should be overridden\n");
+ }
+
+ /**
+ * Sets the number of consecutive store conditional failures.
+ */
+ virtual void setStCondFailures(unsigned int sc_failures) = 0;
+
+ /**
+ * Returns the number of consecutive store conditional failures.
+ */
+ virtual unsigned int readStCondFailures() const = 0;
+
+ /** @} */
+
+ /**
+ * @{
+ * @name SysCall Emulation Interfaces
+ */
+
+ /**
+ * Executes a syscall specified by the callnum.
+ */
+ virtual void syscall(int64_t callnum, Fault *fault) = 0;
+
+ /** @} */