- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
-
- /** Reads the PC. */
- uint64_t readPC();
- /** Reads the NextPC. */
- uint64_t readNextPC();
- /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */
- uint64_t readNextNPC();
-
- /** Sets the PC. */
- void setPC(uint64_t val);
- /** Sets the NextPC. */
- void setNextPC(uint64_t val);
- /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */
- void setNextNPC(uint64_t val);
-
- /** Reads a miscellaneous register. */
- MiscReg readMiscReg(int misc_reg);
-
- /** Reads a miscellaneous register, handling any architectural
- * side effects due to reading that register. */
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
-
- /** Sets a miscellaneous register. */
- Fault setMiscReg(int misc_reg, const MiscReg &val);
-
- /** Sets a miscellaneous register, handling any architectural
- * side effects due to writing that register. */
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
-
- /** Records the effective address of the instruction. Only valid
- * for memory ops. */
- void setEA(Addr EA);
- /** Returns the effective address of the instruction. Only valid
- * for memory ops. */
- Addr getEA();
+ virtual void setFloatRegOperandBits(const StaticInst *si,
+ int idx, FloatRegBits val) = 0;
+
+ /** @} */
+
+ /**
+ * @{
+ * @name Condition Code Registers
+ */
+ virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
+ virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
+ /** @} */
+
+ /**
+ * @{
+ * @name Misc Register Interfaces
+ */
+ virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
+ virtual void setMiscRegOperand(const StaticInst *si,
+ int idx, const MiscReg &val) = 0;
+
+ /**
+ * Reads a miscellaneous register, handling any architectural
+ * side effects due to reading that register.
+ */
+ virtual MiscReg readMiscReg(int misc_reg) = 0;
+
+ /**
+ * Sets a miscellaneous register, handling any architectural
+ * side effects due to writing that register.
+ */
+ virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+
+ /** @} */
+
+ /**
+ * @{
+ * @name PC Control
+ */
+ virtual PCState pcState() const = 0;
+ virtual void pcState(const PCState &val) = 0;
+ /** @} */
+
+ /**
+ * @{
+ * @name Memory Interface
+ */
+ /**
+ * Record the effective address of the instruction.
+ *
+ * @note Only valid for memory ops.
+ */
+ virtual void setEA(Addr EA) = 0;
+ /**
+ * Get the effective address of the instruction.
+ *
+ * @note Only valid for memory ops.
+ */
+ virtual Addr getEA() const = 0;
+
+ virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
+ unsigned int flags) = 0;
+
+ virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
+ unsigned int flags, uint64_t *res) = 0;
+
+ /**
+ * Sets the number of consecutive store conditional failures.
+ */
+ virtual void setStCondFailures(unsigned int sc_failures) = 0;
+
+ /**
+ * Returns the number of consecutive store conditional failures.
+ */
+ virtual unsigned int readStCondFailures() const = 0;
+
+ /** @} */
+
+ /**
+ * @{
+ * @name SysCall Emulation Interfaces
+ */
+
+ /**
+ * Executes a syscall specified by the callnum.
+ */
+ virtual void syscall(int64_t callnum) = 0;
+
+ /** @} */