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cpu: o3: replace issueLatency with bool pipelined
[gem5.git]
/
src
/
cpu
/
kvm
/
base.cc
diff --git
a/src/cpu/kvm/base.cc
b/src/cpu/kvm/base.cc
index 95d91467e402e1e188769c3c029238a63a21cb98..e09c4b7f2c764f5dca30ef35fb8c49debeb140d2 100644
(file)
--- a/
src/cpu/kvm/base.cc
+++ b/
src/cpu/kvm/base.cc
@@
-118,8
+118,6
@@
BaseKvmCPU::init()
// initialize CPU, including PC
if (FullSystem && !switchedOut())
TheISA::initCPU(tc, tc->contextId());
// initialize CPU, including PC
if (FullSystem && !switchedOut())
TheISA::initCPU(tc, tc->contextId());
-
- mmio_req.setThreadContext(tc->contextId(), 0);
}
void
}
void
@@
-995,7
+993,8
@@
BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write)
ThreadContext *tc(thread->getTC());
syncThreadContext();
ThreadContext *tc(thread->getTC());
syncThreadContext();
- mmio_req.setPhys(paddr, size, Request::UNCACHEABLE, dataMasterId());
+ Request mmio_req(paddr, size, Request::UNCACHEABLE, dataMasterId());
+ mmio_req.setThreadContext(tc->contextId(), 0);
// Some architectures do need to massage physical addresses a bit
// before they are inserted into the memory system. This enables
// APIC accesses on x86 and m5ops where supported through a MMIO
// Some architectures do need to massage physical addresses a bit
// before they are inserted into the memory system. This enables
// APIC accesses on x86 and m5ops where supported through a MMIO