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Various serialization changes to make it possible for the O3CPU to checkpoint.
[gem5.git]
/
src
/
cpu
/
o3
/
inst_queue.hh
diff --git
a/src/cpu/o3/inst_queue.hh
b/src/cpu/o3/inst_queue.hh
index 6fd3c6d0b320ddde6f61af1e3639bf4162293bcc..4c69ca3844bcf285745e3b767207ce00c0f97ad5 100644
(file)
--- a/
src/cpu/o3/inst_queue.hh
+++ b/
src/cpu/o3/inst_queue.hh
@@
-26,6
+26,7
@@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#ifndef __CPU_O3_INST_QUEUE_HH__
*/
#ifndef __CPU_O3_INST_QUEUE_HH__
@@
-68,7
+69,7
@@
class InstructionQueue
{
public:
//Typedefs from the Impl.
{
public:
//Typedefs from the Impl.
- typedef typename Impl::
FullCPU Full
CPU;
+ typedef typename Impl::
O3CPU O3
CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
@@
-80,7
+81,7
@@
class InstructionQueue
// Typedef of iterator through the list of instructions.
typedef typename std::list<DynInstPtr>::iterator ListIt;
// Typedef of iterator through the list of instructions.
typedef typename std::list<DynInstPtr>::iterator ListIt;
- friend class Impl::
Full
CPU;
+ friend class Impl::
O3
CPU;
/** FU completion event class. */
class FUCompletion : public Event {
/** FU completion event class. */
class FUCompletion : public Event {
@@
-125,7
+126,7
@@
class InstructionQueue
void resetState();
/** Sets CPU pointer. */
void resetState();
/** Sets CPU pointer. */
- void setCPU(
Full
CPU *_cpu) { cpu = _cpu; }
+ void setCPU(
O3
CPU *_cpu) { cpu = _cpu; }
/** Sets active threads list. */
void setActiveThreads(std::list<unsigned> *at_ptr);
/** Sets active threads list. */
void setActiveThreads(std::list<unsigned> *at_ptr);
@@
-252,7
+253,7
@@
class InstructionQueue
/////////////////////////
/** Pointer to the CPU. */
/////////////////////////
/** Pointer to the CPU. */
-
Full
CPU *cpu;
+
O3
CPU *cpu;
/** Cache interface. */
MemInterface *dcacheInterface;
/** Cache interface. */
MemInterface *dcacheInterface;