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X86: Add a .serializing directive that makes a macroop serializing.
[gem5.git]
/
src
/
cpu
/
ozone
/
front_end_impl.hh
diff --git
a/src/cpu/ozone/front_end_impl.hh
b/src/cpu/ozone/front_end_impl.hh
index 36e87ec9c717fe5aa6524a46babb7d908efd67b7..88413692761484b4dcf82403c931f4a75139530a 100644
(file)
--- a/
src/cpu/ozone/front_end_impl.hh
+++ b/
src/cpu/ozone/front_end_impl.hh
@@
-28,12
+28,12
@@
* Authors: Kevin Lim
*/
* Authors: Kevin Lim
*/
-#include "config/use_checker.hh"
-
-#include "arch/faults.hh"
+#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/statistics.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/statistics.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/front_end.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/front_end.hh"
@@
-91,7
+91,6
@@
template <class Impl>
FrontEnd<Impl>::FrontEnd(Params *params)
: branchPred(params),
icachePort(this),
FrontEnd<Impl>::FrontEnd(Params *params)
: branchPred(params),
icachePort(this),
- mem(params->mem),
numInstsReady(params->frontEndLatency, 0),
instBufferSize(0),
maxInstBufferSize(params->maxInstBufferSize),
numInstsReady(params->frontEndLatency, 0),
instBufferSize(0),
maxInstBufferSize(params->maxInstBufferSize),
@@
-463,15
+462,10
@@
Fault
FrontEnd<Impl>::fetchCacheLine()
{
// Read a cache line, based on the current PC.
FrontEnd<Impl>::fetchCacheLine()
{
// Read a cache line, based on the current PC.
-#if FULL_SYSTEM
- // Flag to say whether or not address is physical addr.
- unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
-#else
- unsigned flags = 0;
-#endif // FULL_SYSTEM
Fault fault = NoFault;
Fault fault = NoFault;
- if (interruptPending && flags == 0) {
+ //AlphaDep
+ if (interruptPending && (PC & 0x3)) {
return fault;
}
return fault;
}
@@
-482,11
+476,11
@@
FrontEnd<Impl>::fetchCacheLine()
// Setup the memReq to do a read of the first isntruction's address.
// Set the appropriate read size and flags as well.
// Setup the memReq to do a read of the first isntruction's address.
// Set the appropriate read size and flags as well.
- memReq = new Request(0, fetch_PC, cacheBlkSize,
flags
,
-
fetch_PC, cpu->readCpuId(), 0
);
+ memReq = new Request(0, fetch_PC, cacheBlkSize,
0
,
+
PC, cpu->thread->contextId()
);
// Translate the instruction request.
// Translate the instruction request.
- fault = cpu->
translateInstReq(memReq, thread
);
+ fault = cpu->
itb->translateAtomic(memReq, thread, false, true
);
// Now do the timing access to see whether or not the instruction
// exists within the cache.
// Now do the timing access to see whether or not the instruction
// exists within the cache.
@@
-883,7
+877,11
@@
FrontEnd<Impl>::getInstFromCacheline()
// Get the instruction from the array of the cache line.
inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
// Get the instruction from the array of the cache line.
inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
+#if THE_ISA == ALPHA_ISA
+ ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
+#elif THE_ISA == SPARC_ISA
ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
+#endif
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),