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X86: Add a .serializing directive that makes a macroop serializing.
[gem5.git]
/
src
/
cpu
/
ozone
/
front_end_impl.hh
diff --git
a/src/cpu/ozone/front_end_impl.hh
b/src/cpu/ozone/front_end_impl.hh
index 6b47ef539c693c7e03e53c1ca31f773bcd179bae..88413692761484b4dcf82403c931f4a75139530a 100644
(file)
--- a/
src/cpu/ozone/front_end_impl.hh
+++ b/
src/cpu/ozone/front_end_impl.hh
@@
-28,12
+28,12
@@
* Authors: Kevin Lim
*/
* Authors: Kevin Lim
*/
-#include "config/use_checker.hh"
-
#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/statistics.hh"
#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/statistics.hh"
+#include "config/the_isa.hh"
+#include "config/use_checker.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/front_end.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/front_end.hh"
@@
-480,7
+480,7
@@
FrontEnd<Impl>::fetchCacheLine()
PC, cpu->thread->contextId());
// Translate the instruction request.
PC, cpu->thread->contextId());
// Translate the instruction request.
- fault = cpu->itb->translateAtomic(memReq, thread);
+ fault = cpu->itb->translateAtomic(memReq, thread
, false, true
);
// Now do the timing access to see whether or not the instruction
// exists within the cache.
// Now do the timing access to see whether or not the instruction
// exists within the cache.