- // translate to physical address
- Fault fault = thread->translateDataWriteReq(req);
-
- // Now do the access.
- if (fault == NoFault) {
- MemCmd cmd = MemCmd::WriteReq; // default
- bool do_access = true; // flag to suppress cache access
-
- if (req->isLocked()) {
- cmd = MemCmd::StoreCondReq;
- do_access = TheISA::handleLockedWrite(thread, req);
- } else if (req->isSwap()) {
- cmd = MemCmd::SwapReq;
- if (req->isCondSwap()) {
- assert(res);
- req->setExtraData(*res);
- }
- }
-
- if (do_access) {
- Packet pkt = Packet(req, cmd, Packet::Broadcast);
- pkt.dataStatic(&data);
-
- if (req->isMmapedIpr()) {
- dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
- } else {
- data = htog(data);
- if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
- dcache_latency = physmemPort.sendAtomic(&pkt);
- else
- dcache_latency = dcachePort.sendAtomic(&pkt);
- }
- dcache_access = true;
- assert(!pkt.isError());
-
- if (req->isSwap()) {
- assert(res);
- *res = pkt.get<T>();
- }
- }
-
- if (res && !req->isSwap()) {
- *res = req->getExtraData();
- }
- }
-
- // This will need a new way to tell if it's hooked up to a cache or not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");