-#define BMIC0 0x0 // Bus master IDE command register
-#define BMIS0 0x2 // Bus master IDE status register
-#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
-#define BMIC1 0x8 // Bus master IDE command register
-#define BMIS1 0xa // Bus master IDE status register
-#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
-
-// Bus master IDE command register bit fields
-#define RWCON 0x08 // Bus master read/write control
-#define SSBM 0x01 // Start/stop bus master
-
-// Bus master IDE status register bit fields
-#define DMA1CAP 0x40 // Drive 1 DMA capable
-#define DMA0CAP 0x20 // Drive 0 DMA capable
-#define IDEINTS 0x04 // IDE Interrupt Status
-#define IDEDMAE 0x02 // IDE DMA error
-#define BMIDEA 0x01 // Bus master IDE active
-
-// IDE Command byte fields
-#define IDE_SELECT_OFFSET (6)
-#define IDE_SELECT_DEV_BIT 0x10
-
-#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
-#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
-
-// IDE Timing Register bit fields
-#define IDETIM_DECODE_EN 0x8000
-
-// PCI device specific register byte offsets
-#define IDE_CTRL_CONF_START 0x40
-#define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
-
-#define IDE_CTRL_CONF_PRIM_TIMING 0x40
-#define IDE_CTRL_CONF_SEC_TIMING 0x42
-#define IDE_CTRL_CONF_DEV_TIMING 0x44
-#define IDE_CTRL_CONF_UDMA_CNTRL 0x48
-#define IDE_CTRL_CONF_UDMA_TIMING 0x4A
-#define IDE_CTRL_CONF_IDE_CONFIG 0x54
-
-
-enum IdeRegType {
- COMMAND_BLOCK,
- CONTROL_BLOCK,
- BMI_BLOCK
-};
-