+
+ case nir_intrinsic_load_vs_primitive_stride_ir3:
+ dst[0] = create_uniform(b, primitive_param + 0);
+ break;
+ case nir_intrinsic_load_vs_vertex_stride_ir3:
+ dst[0] = create_uniform(b, primitive_param + 1);
+ break;
+ case nir_intrinsic_load_hs_patch_stride_ir3:
+ dst[0] = create_uniform(b, primitive_param + 2);
+ break;
+ case nir_intrinsic_load_patch_vertices_in:
+ dst[0] = create_uniform(b, primitive_param + 3);
+ break;
+ case nir_intrinsic_load_tess_param_base_ir3:
+ dst[0] = create_uniform(b, primitive_param + 4);
+ dst[1] = create_uniform(b, primitive_param + 5);
+ break;
+ case nir_intrinsic_load_tess_factor_base_ir3:
+ dst[0] = create_uniform(b, primitive_param + 6);
+ dst[1] = create_uniform(b, primitive_param + 7);
+ break;
+
+ case nir_intrinsic_load_primitive_location_ir3:
+ idx = nir_intrinsic_driver_location(intr);
+ dst[0] = create_uniform(b, primitive_map + idx);
+ break;
+
+ case nir_intrinsic_load_gs_header_ir3:
+ dst[0] = ctx->gs_header;
+ break;
+ case nir_intrinsic_load_tcs_header_ir3:
+ dst[0] = ctx->tcs_header;
+ break;
+
+ case nir_intrinsic_load_primitive_id:
+ dst[0] = ctx->primitive_id;
+ break;
+
+ case nir_intrinsic_load_tess_coord:
+ if (!ctx->tess_coord) {
+ ctx->tess_coord =
+ create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
+ }
+ ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
+
+ /* Unused, but ir3_put_dst() below wants to free something */
+ dst[2] = create_immed(b, 0);
+ break;
+
+ case nir_intrinsic_end_patch_ir3:
+ assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
+ struct ir3_instruction *end = ir3_ENDPATCH(b);
+ array_insert(b, b->keeps, end);
+
+ end->barrier_class = IR3_BARRIER_EVERYTHING;
+ end->barrier_conflict = IR3_BARRIER_EVERYTHING;
+ break;
+
+ case nir_intrinsic_store_global_ir3: {
+ struct ir3_instruction *value, *addr, *offset;
+
+ addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ ir3_get_src(ctx, &intr->src[1])[0],
+ ir3_get_src(ctx, &intr->src[1])[1]
+ }, 2);
+
+ offset = ir3_get_src(ctx, &intr->src[2])[0];
+
+ value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
+ intr->num_components);
+
+ struct ir3_instruction *stg =
+ ir3_STG_G(ctx->block, addr, 0, value, 0,
+ create_immed(ctx->block, intr->num_components), 0, offset, 0);
+ stg->cat6.type = TYPE_U32;
+ stg->cat6.iim_val = 1;
+
+ array_insert(b, b->keeps, stg);
+
+ stg->barrier_class = IR3_BARRIER_BUFFER_W;
+ stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
+ break;
+ }
+
+ case nir_intrinsic_load_global_ir3: {
+ struct ir3_instruction *addr, *offset;
+
+ addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
+ ir3_get_src(ctx, &intr->src[0])[0],
+ ir3_get_src(ctx, &intr->src[0])[1]
+ }, 2);
+
+ offset = ir3_get_src(ctx, &intr->src[1])[0];
+
+ struct ir3_instruction *load =
+ ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
+ 0, offset, 0);
+ load->cat6.type = TYPE_U32;
+ load->regs[0]->wrmask = MASK(intr->num_components);
+
+ load->barrier_class = IR3_BARRIER_BUFFER_R;
+ load->barrier_conflict = IR3_BARRIER_BUFFER_W;
+
+ ir3_split_dest(b, dst, load, 0, intr->num_components);
+ break;
+ }
+