+ unsigned num_precolor = 0;
+ for (unsigned i = 0; i < nprecolor; i++) {
+ if (precolor[i] && !(precolor[i]->flags & IR3_INSTR_UNUSED)) {
+ struct ir3_instruction *instr = precolor[i];
+ struct ir3_ra_instr_data *id = &ctx->instrd[instr->ip];
+
+ debug_assert(!(instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_HIGH)));
+
+ /* only consider the first component: */
+ if (id->off > 0)
+ continue;
+
+ /* 'base' is in scalar (class 0) but we need to map that
+ * the conflicting register of the appropriate class (ie.
+ * input could be vec2/vec3/etc)
+ *
+ * Note that the higher class (larger than scalar) regs
+ * are setup to conflict with others in the same class,
+ * so for example, R1 (scalar) is also the first component
+ * of D1 (vec2/double):
+ *
+ * Single (base) | Double
+ * --------------+---------------
+ * R0 | D0
+ * R1 | D0 D1
+ * R2 | D1 D2
+ * R3 | D2
+ * .. and so on..
+ */
+ unsigned regid = instr->regs[0]->num;
+ unsigned reg = ctx->set->gpr_to_ra_reg[id->cls][regid];
+ unsigned name = ra_name(ctx, id);
+ ra_set_node_reg(ctx->g, name, reg);
+ num_precolor = MAX2(regid, num_precolor);
+ }
+ }
+