+
+ if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
+ foreach_array (arr, &ctx->ir->array_list) {
+ unsigned first = arr->reg;
+ unsigned last = arr->reg + arr->length - 1;
+ debug_printf("arr[%d] at r%d.%c->r%d.%c\n", arr->id,
+ (first >> 2), "xyzw"[first & 0x3],
+ (last >> 2), "xyzw"[last & 0x3]);
+ }
+ }
+}
+
+static void
+precolor(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr)
+{
+ struct ir3_ra_instr_data *id = &ctx->instrd[instr->ip];
+ unsigned n = dest_regs(instr);
+ for (unsigned i = 0; i < n; i++) {
+ /* tex instructions actually have a wrmask, and
+ * don't touch masked out components. So we
+ * shouldn't precolor them::
+ */
+ if (is_tex_or_prefetch(instr) &&
+ !(instr->regs[0]->wrmask & (1 << i)))
+ continue;
+
+ unsigned name = scalar_name(ctx, instr, i);
+ unsigned regid = instr->regs[0]->num + i;
+
+ if (instr->regs[0]->flags & IR3_REG_HIGH)
+ regid -= FIRST_HIGH_REG;
+
+ unsigned vreg = ctx->set->gpr_to_ra_reg[id->cls][regid];
+ ra_set_node_reg(ctx->g, name, vreg);
+ }
+}
+
+/* pre-color non-scalar registers based on the registers assigned in previous
+ * pass. Do this by looking actually at the fanout instructions.
+ */
+static void
+ra_precolor_assigned(struct ir3_ra_ctx *ctx)
+{
+ debug_assert(ctx->scalar_pass);
+
+ foreach_block (block, &ctx->ir->block_list) {
+ foreach_instr (instr, &block->instr_list) {
+
+ if ((instr->opc != OPC_META_SPLIT) &&
+ (instr->opc != OPC_META_COLLECT))
+ continue;
+
+ precolor(ctx, instr);
+
+ struct ir3_register *src;
+ foreach_src (src, instr) {
+ if (!src->instr)
+ continue;
+ precolor(ctx, src->instr);
+ }
+ }
+ }