- for (unsigned i = 0; i < count; i++) {
- q_values[i + off] = rzalloc_array(q_values, unsigned, total_class_count);
-
- /* From register_allocate.c:
- *
- * q(B,C) (indexed by C, B is this register class) in
- * Runeson/Nyström paper. This is "how many registers of B could
- * the worst choice register from C conflict with".
- *
- * If we just let the register allocation algorithm compute these
- * values, is extremely expensive. However, since all of our
- * registers are laid out, we can very easily compute them
- * ourselves. View the register from C as fixed starting at GRF n
- * somewhere in the middle, and the register from B as sliding back
- * and forth. Then the first register to conflict from B is the
- * one starting at n - class_size[B] + 1 and the last register to
- * conflict will start at n + class_size[B] - 1. Therefore, the
- * number of conflicts from B is class_size[B] + class_size[C] - 1.
- *
- * +-+-+-+-+-+-+ +-+-+-+-+-+-+
- * B | | | | | |n| --> | | | | | | |
- * +-+-+-+-+-+-+ +-+-+-+-+-+-+
- * +-+-+-+-+-+
- * C |n| | | | |
- * +-+-+-+-+-+
- *
- * (Idea copied from brw_fs_reg_allocate.cpp)
- */
- for (unsigned j = 0; j < count; j++)
- q_values[i + off][j + off] = sizes[i] + sizes[j] - 1;
+ unsigned reg;
+
+ reg = 0;
+ for (unsigned i = 0; i < class_count; i++) {
+ for (unsigned j = 0; j < CLASS_REGS(i); j++) {
+ for (unsigned br = j; br < j + class_sizes[i]; br++) {
+ ra_add_transitive_reg_conflict(set->regs, br, reg);
+ }
+
+ reg++;
+ }
+ }
+
+ for (unsigned i = 0; i < half_class_count; i++) {
+ for (unsigned j = 0; j < HALF_CLASS_REGS(i); j++) {
+ for (unsigned br = j; br < j + half_class_sizes[i]; br++) {
+ ra_add_transitive_reg_conflict(set->regs,
+ br + set->first_half_reg, reg);
+ }
+
+ reg++;
+ }
+ }
+
+ for (unsigned i = 0; i < high_class_count; i++) {
+ for (unsigned j = 0; j < HIGH_CLASS_REGS(i); j++) {
+ for (unsigned br = j; br < j + high_class_sizes[i]; br++) {
+ ra_add_transitive_reg_conflict(set->regs,
+ br + set->first_high_reg, reg);
+ }
+
+ reg++;
+ }
+ }
+
+ /*
+ * Setup conflicts with registers over 0x3f for the special vreg
+ * that exists to use as interference for tex-prefetch:
+ */
+
+ for (unsigned i = 0x40; i < CLASS_REGS(0); i++) {
+ ra_add_transitive_reg_conflict(set->regs, i,
+ set->prefetch_exclude_reg);
+ }
+
+ for (unsigned i = 0x40; i < HALF_CLASS_REGS(0); i++) {
+ ra_add_transitive_reg_conflict(set->regs, i + set->first_half_reg,
+ set->prefetch_exclude_reg);