+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+ const struct tu_image_view *iview = fb->attachments[a].attachment;
+ const struct tu_render_pass_attachment *attachment =
+ &cmd->state.pass->attachments[a];
+ unsigned clear_mask = 0;
+
+ /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
+ if (attachment->gmem_offset < 0)
+ return;
+
+ if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
+ clear_mask = 0xf;
+ }
+
+ if (vk_format_has_stencil(iview->vk_format)) {
+ clear_mask &= 0x1;
+ if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
+ clear_mask |= 0x2;
+ if (clear_mask != 0x3)
+ tu_finishme("depth/stencil only load op");
+ }
+
+ if (!clear_mask)
+ return;
+
+ tu_clear_sysmem_attachment(cmd, cs, a,
+ &info->pClearValues[a], &(struct VkClearRect) {
+ .rect = info->renderArea,
+ .baseArrayLayer = iview->base_layer,
+ .layerCount = iview->layer_count,
+ });
+}
+
+static void
+tu_cmd_prepare_sysmem_clear_ib(struct tu_cmd_buffer *cmd,
+ const VkRenderPassBeginInfo *info)
+{
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+ const uint32_t blit_cmd_space = 25 + 66 * fb->layers + 17;
+ const uint32_t clear_space =
+ blit_cmd_space * cmd->state.pass->attachment_count + 5;
+
+ struct tu_cs sub_cs;
+
+ VkResult result =
+ tu_cs_begin_sub_stream(&cmd->sub_cs, clear_space, &sub_cs);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
+
+ for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
+ tu_emit_sysmem_clear_attachment(cmd, &sub_cs, i, info);
+
+ /* TODO: We shouldn't need this flush, but without it we'd have an empty IB
+ * when nothing clears which we currently can't handle.
+ */
+ tu_cs_reserve_space(&sub_cs, 5);
+ tu6_emit_event_write(cmd, &sub_cs, PC_CCU_FLUSH_COLOR_TS, true);
+
+ cmd->state.sysmem_clear_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
+}
+
+static void
+tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
+ const struct VkRect2D *renderArea)
+{
+ VkResult result = tu_cs_reserve_space(cs, 1024);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
+
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+ if (fb->width > 0 && fb->height > 0) {
+ tu6_emit_window_scissor(cmd, cs,
+ 0, 0, fb->width - 1, fb->height - 1);
+ } else {
+ tu6_emit_window_scissor(cmd, cs, 0, 0, 0, 0);
+ }
+
+ tu6_emit_window_offset(cmd, cs, 0, 0);
+
+ tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
+
+ tu_cs_emit_ib(cs, &cmd->state.sysmem_clear_ib);
+
+ tu6_emit_lrz_flush(cmd, cs);
+
+ tu6_emit_marker(cmd, cs);
+ tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
+ tu6_emit_marker(cmd, cs);
+
+ tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
+ tu_cs_emit(cs, 0x0);
+
+ tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
+ tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
+ tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
+
+ tu6_emit_wfi(cmd, cs);
+ tu_cs_emit_regs(cs,
+ A6XX_RB_CCU_CNTL(0x10000000));
+
+ /* enable stream-out, with sysmem there is only one pass: */
+ tu_cs_emit_regs(cs,
+ A6XX_VPC_SO_OVERRIDE(.so_disable = false));
+
+ tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
+ tu_cs_emit(cs, 0x1);
+
+ tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
+ tu_cs_emit(cs, 0x0);
+
+ tu_cs_sanity_check(cs);
+}
+
+static void
+tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
+{
+ /* Do any resolves of the last subpass. These are handled in the
+ * tile_store_ib in the gmem path.
+ */
+