- if (swizzle == TGSI_EXTSWIZZLE_ONE) {
- /* Load const one float and early out */
- reg = get_const_one_reg(gen);
- }
- else if (swizzle == TGSI_EXTSWIZZLE_ZERO) {
- /* Load const zero float and early out */
- reg = get_itemp(gen);
- spe_xor(gen->f, reg, reg, reg);
- }
- else {