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Merge branch '7.8'
[mesa.git]
/
src
/
gallium
/
drivers
/
cell
/
spu
/
spu_exec.c
diff --git
a/src/gallium/drivers/cell/spu/spu_exec.c
b/src/gallium/drivers/cell/spu/spu_exec.c
index 0eaae2e451bc12258b213931fb5302cfa3988250..d7788bd9bbbc129e903ac0f01d3b9242ed2b1d62 100644
(file)
--- a/
src/gallium/drivers/cell/spu/spu_exec.c
+++ b/
src/gallium/drivers/cell/spu/spu_exec.c
@@
-108,10
+108,10
@@
for (CHAN = 0; CHAN < 4; CHAN++)
#define IS_CHANNEL_ENABLED(INST, CHAN)\
for (CHAN = 0; CHAN < 4; CHAN++)
#define IS_CHANNEL_ENABLED(INST, CHAN)\
- ((INST).
FullDstRegisters[0].Dst
Register.WriteMask & (1 << (CHAN)))
+ ((INST).
Dst[0].
Register.WriteMask & (1 << (CHAN)))
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
- ((INST).
FullDstRegisters[1].Dst
Register.WriteMask & (1 << (CHAN)))
+ ((INST).
Dst[1].
Register.WriteMask & (1 << (CHAN)))
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
FOR_EACH_CHANNEL( CHAN )\
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
FOR_EACH_CHANNEL( CHAN )\
@@
-346,10
+346,10
@@
fetch_src_file_channel(
union spu_exec_channel *chan )
{
switch( swizzle ) {
union spu_exec_channel *chan )
{
switch( swizzle ) {
- case TGSI_
EXT
SWIZZLE_X:
- case TGSI_
EXT
SWIZZLE_Y:
- case TGSI_
EXT
SWIZZLE_Z:
- case TGSI_
EXT
SWIZZLE_W:
+ case TGSI_SWIZZLE_X:
+ case TGSI_SWIZZLE_Y:
+ case TGSI_SWIZZLE_Z:
+ case TGSI_SWIZZLE_W:
switch( file ) {
case TGSI_FILE_CONSTANT: {
unsigned i;
switch( file ) {
case TGSI_FILE_CONSTANT: {
unsigned i;
@@
-413,14
+413,6
@@
fetch_src_file_channel(
}
break;
}
break;
- case TGSI_EXTSWIZZLE_ZERO:
- *chan = mach->Temps[TEMP_0_I].xyzw[TEMP_0_C];
- break;
-
- case TGSI_EXTSWIZZLE_ONE:
- *chan = mach->Temps[TEMP_1_I].xyzw[TEMP_1_C];
- break;
-
default:
ASSERT( 0 );
}
default:
ASSERT( 0 );
}
@@
-439,22
+431,22
@@
fetch_source(
index.i[0] =
index.i[1] =
index.i[2] =
index.i[0] =
index.i[1] =
index.i[2] =
- index.i[3] = reg->
Src
Register.Index;
+ index.i[3] = reg->Register.Index;
- if (reg->
Src
Register.Indirect) {
+ if (reg->Register.Indirect) {
union spu_exec_channel index2;
union spu_exec_channel indir_index;
index2.i[0] =
index2.i[1] =
index2.i[2] =
union spu_exec_channel index2;
union spu_exec_channel indir_index;
index2.i[0] =
index2.i[1] =
index2.i[2] =
- index2.i[3] = reg->
SrcRegisterInd
.Index;
+ index2.i[3] = reg->
Indirect
.Index;
- swizzle = tgsi_util_get_src_register_swizzle(®->
SrcRegisterInd
,
+ swizzle = tgsi_util_get_src_register_swizzle(®->
Indirect
,
CHAN_X);
fetch_src_file_channel(
mach,
CHAN_X);
fetch_src_file_channel(
mach,
- reg->
SrcRegisterInd
.File,
+ reg->
Indirect
.File,
swizzle,
&index2,
&indir_index );
swizzle,
&index2,
&indir_index );
@@
-462,8
+454,8
@@
fetch_source(
index.q = si_a(index.q, indir_index.q);
}
index.q = si_a(index.q, indir_index.q);
}
- if( reg->
Src
Register.Dimension ) {
- switch( reg->
Src
Register.File ) {
+ if( reg->Register.Dimension ) {
+ switch( reg->Register.File ) {
case TGSI_FILE_INPUT:
index.q = si_mpyi(index.q, 17);
break;
case TGSI_FILE_INPUT:
index.q = si_mpyi(index.q, 17);
break;
@@
-474,24
+466,24
@@
fetch_source(
ASSERT( 0 );
}
ASSERT( 0 );
}
- index.i[0] += reg->
SrcRegisterDim
.Index;
- index.i[1] += reg->
SrcRegisterDim
.Index;
- index.i[2] += reg->
SrcRegisterDim
.Index;
- index.i[3] += reg->
SrcRegisterDim
.Index;
+ index.i[0] += reg->
Dimension
.Index;
+ index.i[1] += reg->
Dimension
.Index;
+ index.i[2] += reg->
Dimension
.Index;
+ index.i[3] += reg->
Dimension
.Index;
- if (reg->
SrcRegisterDim
.Indirect) {
+ if (reg->
Dimension
.Indirect) {
union spu_exec_channel index2;
union spu_exec_channel indir_index;
index2.i[0] =
index2.i[1] =
index2.i[2] =
union spu_exec_channel index2;
union spu_exec_channel indir_index;
index2.i[0] =
index2.i[1] =
index2.i[2] =
- index2.i[3] = reg->
SrcRegisterDimInd
.Index;
+ index2.i[3] = reg->
DimIndirect
.Index;
- swizzle = tgsi_util_get_src_register_swizzle( ®->
SrcRegisterDimInd
, CHAN_X );
+ swizzle = tgsi_util_get_src_register_swizzle( ®->
DimIndirect
, CHAN_X );
fetch_src_file_channel(
mach,
fetch_src_file_channel(
mach,
- reg->
SrcRegisterDimInd
.File,
+ reg->
DimIndirect
.File,
swizzle,
&index2,
&indir_index );
swizzle,
&index2,
&indir_index );
@@
-500,10
+492,10
@@
fetch_source(
}
}
}
}
- swizzle = tgsi_util_get_full_src_register_
ext
swizzle( reg, chan_index );
+ swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
fetch_src_file_channel(
mach,
fetch_src_file_channel(
mach,
- reg->
Src
Register.File,
+ reg->Register.File,
swizzle,
&index,
chan );
swizzle,
&index,
chan );
@@
-525,7
+517,7
@@
fetch_source(
break;
}
break;
}
- if (reg->
Src
RegisterExtMod.Complement) {
+ if (reg->RegisterExtMod.Complement) {
chan->q = si_fs(mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].q, chan->q);
}
}
chan->q = si_fs(mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].q, chan->q);
}
}
@@
-540,21
+532,21
@@
store_dest(
{
union spu_exec_channel *dst;
{
union spu_exec_channel *dst;
- switch( reg->
Dst
Register.File ) {
+ switch( reg->Register.File ) {
case TGSI_FILE_NULL:
return;
case TGSI_FILE_OUTPUT:
dst = &mach->Outputs[mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
case TGSI_FILE_NULL:
return;
case TGSI_FILE_OUTPUT:
dst = &mach->Outputs[mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
- + reg->
Dst
Register.Index].xyzw[chan_index];
+ + reg->Register.Index].xyzw[chan_index];
break;
case TGSI_FILE_TEMPORARY:
break;
case TGSI_FILE_TEMPORARY:
- dst = &mach->Temps[reg->
Dst
Register.Index].xyzw[chan_index];
+ dst = &mach->Temps[reg->Register.Index].xyzw[chan_index];
break;
case TGSI_FILE_ADDRESS:
break;
case TGSI_FILE_ADDRESS:
- dst = &mach->Addrs[reg->
Dst
Register.Index].xyzw[chan_index];
+ dst = &mach->Addrs[reg->Register.Index].xyzw[chan_index];
break;
default:
break;
default:
@@
-591,10
+583,10
@@
store_dest(
}
#define FETCH(VAL,INDEX,CHAN)\
}
#define FETCH(VAL,INDEX,CHAN)\
- fetch_source (mach, VAL, &inst->
FullSrcRegisters
[INDEX], CHAN)
+ fetch_source (mach, VAL, &inst->
Src
[INDEX], CHAN)
#define STORE(VAL,INDEX,CHAN)\
#define STORE(VAL,INDEX,CHAN)\
- store_dest (mach, VAL, &inst->
FullDstRegisters
[INDEX], inst, CHAN )
+ store_dest (mach, VAL, &inst->
Dst
[INDEX], inst, CHAN )
/**
/**
@@
-610,10
+602,8
@@
exec_kil(struct spu_exec_machine *mach,
uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
union spu_exec_channel r[1];
uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
union spu_exec_channel r[1];
- /* This mask stores component bits that were already tested. Note that
- * we test if the value is less than zero, so 1.0 and 0.0 need not to be
- * tested. */
- uniquemask = (1 << TGSI_EXTSWIZZLE_ZERO) | (1 << TGSI_EXTSWIZZLE_ONE);
+ /* This mask stores component bits that were already tested. */
+ uniquemask = 0;
for (chan_index = 0; chan_index < 4; chan_index++)
{
for (chan_index = 0; chan_index < 4; chan_index++)
{
@@
-621,8
+611,8
@@
exec_kil(struct spu_exec_machine *mach,
uint i;
/* unswizzle channel */
uint i;
/* unswizzle channel */
- swizzle = tgsi_util_get_full_src_register_
ext
swizzle (
- &inst->
FullSrcRegisters
[0],
+ swizzle = tgsi_util_get_full_src_register_swizzle (
+ &inst->
Src
[0],
chan_index);
/* check if the component has not been already tested */
chan_index);
/* check if the component has not been already tested */
@@
-687,7
+677,7
@@
exec_tex(struct spu_exec_machine *mach,
const struct tgsi_full_instruction *inst,
boolean biasLod, boolean projected)
{
const struct tgsi_full_instruction *inst,
boolean biasLod, boolean projected)
{
- const uint unit = inst->
FullSrcRegisters[1].Src
Register.Index;
+ const uint unit = inst->
Src[1].
Register.Index;
union spu_exec_channel r[8];
uint chan_index;
float lodBias;
union spu_exec_channel r[8];
uint chan_index;
float lodBias;
@@
-843,8
+833,8
@@
exec_declaration(struct spu_exec_machine *mach,
unsigned first, last, mask;
interpolation_func interp;
unsigned first, last, mask;
interpolation_func interp;
- first = decl->
Declaration
Range.First;
- last = decl->
Declaration
Range.Last;
+ first = decl->Range.First;
+ last = decl->Range.Last;
mask = decl->Declaration.UsageMask;
switch( decl->Declaration.Interpolate ) {
mask = decl->Declaration.UsageMask;
switch( decl->Declaration.Interpolate ) {
@@
-909,7
+899,6
@@
exec_instruction(
break;
case TGSI_OPCODE_MOV:
break;
case TGSI_OPCODE_MOV:
- case TGSI_OPCODE_SWZ:
FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
FETCH( &r[0], 0, chan_index );
STORE( &r[0], 0, chan_index );
FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
FETCH( &r[0], 0, chan_index );
STORE( &r[0], 0, chan_index );
@@
-1633,14
+1622,6
@@
exec_instruction(
*pc = -1;
break;
*pc = -1;
break;
- case TGSI_OPCODE_REP:
- ASSERT (0);
- break;
-
- case TGSI_OPCODE_ENDREP:
- ASSERT (0);
- break;
-
case TGSI_OPCODE_PUSHA:
ASSERT (0);
break;
case TGSI_OPCODE_PUSHA:
ASSERT (0);
break;
@@
-1692,7
+1673,7
@@
exec_instruction(
}
break;
}
break;
- case TGSI_OPCODE_SHR:
+ case TGSI_OPCODE_
I
SHR:
FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
FETCH( &r[0], 0, chan_index );
FETCH( &r[1], 1, chan_index );
FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
FETCH( &r[0], 0, chan_index );
FETCH( &r[1], 1, chan_index );
@@
-1754,8
+1735,6
@@
exec_instruction(
mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] = 0;
break;
mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] = 0;
break;
- case TGSI_OPCODE_BGNFOR:
- /* fall-through (for now) */
case TGSI_OPCODE_BGNLOOP:
/* push LoopMask and ContMasks */
ASSERT(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
case TGSI_OPCODE_BGNLOOP:
/* push LoopMask and ContMasks */
ASSERT(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
@@
-1764,8
+1743,6
@@
exec_instruction(
mach->ContStack[mach->ContStackTop++] = mach->ContMask;
break;
mach->ContStack[mach->ContStackTop++] = mach->ContMask;
break;
- case TGSI_OPCODE_ENDFOR:
- /* fall-through (for now at least) */
case TGSI_OPCODE_ENDLOOP:
/* Restore ContMask, but don't pop */
ASSERT(mach->ContStackTop > 0);
case TGSI_OPCODE_ENDLOOP:
/* Restore ContMask, but don't pop */
ASSERT(mach->ContStackTop > 0);
@@
-1807,22
+1784,6
@@
exec_instruction(
/* no-op */
break;
/* no-op */
break;
- case TGSI_OPCODE_NOISE1:
- ASSERT( 0 );
- break;
-
- case TGSI_OPCODE_NOISE2:
- ASSERT( 0 );
- break;
-
- case TGSI_OPCODE_NOISE3:
- ASSERT( 0 );
- break;
-
- case TGSI_OPCODE_NOISE4:
- ASSERT( 0 );
- break;
-
case TGSI_OPCODE_NOP:
break;
case TGSI_OPCODE_NOP:
break;
@@
-1866,10
+1827,11
@@
spu_exec_machine_run( struct spu_exec_machine *mach )
/* execute declarations (interpolants) */
if( mach->Processor == TGSI_PROCESSOR_FRAGMENT ) {
for (i = 0; i < mach->NumDeclarations; i++) {
/* execute declarations (interpolants) */
if( mach->Processor == TGSI_PROCESSOR_FRAGMENT ) {
for (i = 0; i < mach->NumDeclarations; i++) {
+ PIPE_ALIGN_VAR(16)
union {
struct tgsi_full_declaration decl;
qword buffer[ROUNDUP16(sizeof(struct tgsi_full_declaration)) / 16];
union {
struct tgsi_full_declaration decl;
qword buffer[ROUNDUP16(sizeof(struct tgsi_full_declaration)) / 16];
- } d
ALIGN16_ATTRIB
;
+ } d;
unsigned ea = (unsigned) (mach->Declarations + pc);
spu_dcache_fetch_unaligned(d.buffer, ea, sizeof(d.decl));
unsigned ea = (unsigned) (mach->Declarations + pc);
spu_dcache_fetch_unaligned(d.buffer, ea, sizeof(d.decl));
@@
-1880,10
+1842,11
@@
spu_exec_machine_run( struct spu_exec_machine *mach )
/* execute instructions, until pc is set to -1 */
while (pc != -1) {
/* execute instructions, until pc is set to -1 */
while (pc != -1) {
+ PIPE_ALIGN_VAR(16)
union {
struct tgsi_full_instruction inst;
qword buffer[ROUNDUP16(sizeof(struct tgsi_full_instruction)) / 16];
union {
struct tgsi_full_instruction inst;
qword buffer[ROUNDUP16(sizeof(struct tgsi_full_instruction)) / 16];
- } i
ALIGN16_ATTRIB
;
+ } i;
unsigned ea = (unsigned) (mach->Instructions + pc);
spu_dcache_fetch_unaligned(i.buffer, ea, sizeof(i.inst));
unsigned ea = (unsigned) (mach->Instructions + pc);
spu_dcache_fetch_unaligned(i.buffer, ea, sizeof(i.inst));