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etnaviv: detect v4 compression
[mesa.git]
/
src
/
gallium
/
drivers
/
etnaviv
/
etnaviv_internal.h
diff --git
a/src/gallium/drivers/etnaviv/etnaviv_internal.h
b/src/gallium/drivers/etnaviv/etnaviv_internal.h
index b8d21864331138db14438d7704ad2b92d649050a..27b6c3b28e7b3a8cfe989d023451a438525a5c7d 100644
(file)
--- a/
src/gallium/drivers/etnaviv/etnaviv_internal.h
+++ b/
src/gallium/drivers/etnaviv/etnaviv_internal.h
@@
-31,7
+31,7
@@
#include "hw/state.xml.h"
#include "hw/state_3d.xml.h"
#include "hw/state.xml.h"
#include "hw/state_3d.xml.h"
-#include
<etnaviv_drmif.h>
+#include
"drm/etnaviv_drmif.h"
#define ETNA_NUM_INPUTS (16)
#define ETNA_NUM_VARYINGS 8
#define ETNA_NUM_INPUTS (16)
#define ETNA_NUM_VARYINGS 8
@@
-76,6
+76,8
@@
struct etna_specs {
unsigned has_new_transcendentals : 1;
/* has the new dp2/dpX_norm instructions, among others */
unsigned has_halti2_instructions : 1;
unsigned has_new_transcendentals : 1;
/* has the new dp2/dpX_norm instructions, among others */
unsigned has_halti2_instructions : 1;
+ /* has V4_COMPRESSION */
+ unsigned v4_compression : 1;
/* supports single-buffer rendering with multiple pixel pipes */
unsigned single_buffer : 1;
/* has unified uniforms memory */
/* supports single-buffer rendering with multiple pixel pipes */
unsigned single_buffer : 1;
/* has unified uniforms memory */
@@
-87,7
+89,7
@@
struct etna_specs {
/* has BLT engine instead of RS */
unsigned use_blt : 1;
/* can use any kind of wrapping mode on npot textures */
/* has BLT engine instead of RS */
unsigned use_blt : 1;
/* can use any kind of wrapping mode on npot textures */
- unsigned npot_tex_any_wrap;
+ unsigned npot_tex_any_wrap
: 1
;
/* number of bits per TS tile */
unsigned bits_per_tile;
/* clear value for TS (dependent on bits_per_tile) */
/* number of bits per TS tile */
unsigned bits_per_tile;
/* clear value for TS (dependent on bits_per_tile) */
@@
-182,7
+184,6
@@
struct compiled_viewport_state {
/* Compiled pipe_framebuffer_state */
struct compiled_framebuffer_state {
/* Compiled pipe_framebuffer_state */
struct compiled_framebuffer_state {
- struct pipe_surface *cbuf, *zsbuf; /* keep reference to surfaces */
uint32_t GL_MULTI_SAMPLE_CONFIG;
uint32_t PE_COLOR_FORMAT;
uint32_t PE_DEPTH_CONFIG;
uint32_t GL_MULTI_SAMPLE_CONFIG;
uint32_t PE_COLOR_FORMAT;
uint32_t PE_DEPTH_CONFIG;
@@
-194,6
+195,7
@@
struct compiled_framebuffer_state {
struct etna_reloc PE_COLOR_ADDR;
struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
uint32_t PE_COLOR_STRIDE;
struct etna_reloc PE_COLOR_ADDR;
struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
uint32_t PE_COLOR_STRIDE;
+ uint32_t PE_MEM_CONFIG;
uint32_t SE_SCISSOR_LEFT;
uint32_t SE_SCISSOR_TOP;
uint32_t SE_SCISSOR_RIGHT;
uint32_t SE_SCISSOR_LEFT;
uint32_t SE_SCISSOR_TOP;
uint32_t SE_SCISSOR_RIGHT;
@@
-271,12
+273,6
@@
struct compiled_shader_state {
/* state of some 3d and common registers relevant to etna driver */
struct etna_3d_state {
/* state of some 3d and common registers relevant to etna driver */
struct etna_3d_state {
- unsigned vs_uniforms_size;
- unsigned ps_uniforms_size;
-
- uint32_t /*01008*/ PS_INPUT_COUNT;
- uint32_t /*0100C*/ PS_TEMP_REGISTER_CONTROL;
- uint32_t /*03818*/ GL_MULTI_SAMPLE_CONFIG;
uint32_t /*05000*/ VS_UNIFORMS[VIVS_VS_UNIFORMS__LEN];
uint32_t /*07000*/ PS_UNIFORMS[VIVS_PS_UNIFORMS__LEN];
};
uint32_t /*05000*/ VS_UNIFORMS[VIVS_VS_UNIFORMS__LEN];
uint32_t /*07000*/ PS_UNIFORMS[VIVS_PS_UNIFORMS__LEN];
};