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svga: Adjust alpha for S3TC_DXT1_EXT RGB formats
[mesa.git]
/
src
/
gallium
/
drivers
/
freedreno
/
freedreno_draw.h
diff --git
a/src/gallium/drivers/freedreno/freedreno_draw.h
b/src/gallium/drivers/freedreno/freedreno_draw.h
index 7a970a28b316ba4a8221dc5f9115932a3a09af6d..b293f73b82ed4f4f89f037df3d7f5d084d97db9b 100644
(file)
--- a/
src/gallium/drivers/freedreno/freedreno_draw.h
+++ b/
src/gallium/drivers/freedreno/freedreno_draw.h
@@
-42,7
+42,7
@@
struct fd_ringbuffer;
void fd_draw_init(struct pipe_context *pctx);
static inline void
void fd_draw_init(struct pipe_context *pctx);
static inline void
-fd_draw(struct fd_
context *ctx
, struct fd_ringbuffer *ring,
+fd_draw(struct fd_
batch *batch
, struct fd_ringbuffer *ring,
enum pc_di_primtype primtype,
enum pc_di_vis_cull_mode vismode,
enum pc_di_src_sel src_sel, uint32_t count,
enum pc_di_primtype primtype,
enum pc_di_vis_cull_mode vismode,
enum pc_di_src_sel src_sel, uint32_t count,
@@
-59,7
+59,7
@@
fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
*/
emit_marker(ring, 7);
*/
emit_marker(ring, 7);
- if (is_a3xx_p0(ctx->screen)) {
+ if (is_a3xx_p0(
batch->
ctx->screen)) {
/* dummy-draw workaround: */
OUT_PKT3(ring, CP_DRAW_INDX, 3);
OUT_RING(ring, 0x00000000);
/* dummy-draw workaround: */
OUT_PKT3(ring, CP_DRAW_INDX, 3);
OUT_RING(ring, 0x00000000);
@@
-81,7
+81,7
@@
fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
* we know if we are binning or not
*/
OUT_RINGP(ring, DRAW(primtype, src_sel, idx_type, 0, instances),
* we know if we are binning or not
*/
OUT_RINGP(ring, DRAW(primtype, src_sel, idx_type, 0, instances),
- &
ctx
->draw_patches);
+ &
batch
->draw_patches);
} else {
OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode, instances));
}
} else {
OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode, instances));
}
@@
-93,7
+93,7
@@
fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
emit_marker(ring, 7);
emit_marker(ring, 7);
- fd_reset_wfi(
ctx
);
+ fd_reset_wfi(
batch
);
}
}
@@
-112,24
+112,24
@@
size2indextype(unsigned index_size)
/* this is same for a2xx/a3xx, so split into helper: */
static inline void
/* this is same for a2xx/a3xx, so split into helper: */
static inline void
-fd_draw_emit(struct fd_
context *ctx
, struct fd_ringbuffer *ring,
+fd_draw_emit(struct fd_
batch *batch
, struct fd_ringbuffer *ring,
enum pc_di_primtype primtype,
enum pc_di_vis_cull_mode vismode,
enum pc_di_primtype primtype,
enum pc_di_vis_cull_mode vismode,
- const struct pipe_draw_info *info)
+ const struct pipe_draw_info *info,
+ unsigned index_offset)
{
{
- struct pipe_index_buffer *idx = &ctx->indexbuf;
struct pipe_resource *idx_buffer = NULL;
enum pc_di_index_size idx_type = INDEX_SIZE_IGN;
enum pc_di_src_sel src_sel;
uint32_t idx_size, idx_offset;
struct pipe_resource *idx_buffer = NULL;
enum pc_di_index_size idx_type = INDEX_SIZE_IGN;
enum pc_di_src_sel src_sel;
uint32_t idx_size, idx_offset;
- if (info->index
ed
) {
- assert(!i
dx->user_buffer
);
+ if (info->index
_size
) {
+ assert(!i
nfo->has_user_indices
);
- idx_buffer = i
dx->buffer
;
- idx_type = size2indextype(i
dx
->index_size);
- idx_size = i
dx
->index_size * info->count;
- idx_offset = i
dx->offset + (info->start * idx->index_size)
;
+ idx_buffer = i
nfo->index.resource
;
+ idx_type = size2indextype(i
nfo
->index_size);
+ idx_size = i
nfo
->index_size * info->count;
+ idx_offset = i
ndex_offset + info->start * info->index_size
;
src_sel = DI_SRC_SEL_DMA;
} else {
idx_buffer = NULL;
src_sel = DI_SRC_SEL_DMA;
} else {
idx_buffer = NULL;
@@
-139,7
+139,7
@@
fd_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
src_sel = DI_SRC_SEL_AUTO_INDEX;
}
src_sel = DI_SRC_SEL_AUTO_INDEX;
}
- fd_draw(
ctx
, ring, primtype, vismode, src_sel,
+ fd_draw(
batch
, ring, primtype, vismode, src_sel,
info->count, info->instance_count - 1,
idx_type, idx_size, idx_offset, idx_buffer);
}
info->count, info->instance_count - 1,
idx_type, idx_size, idx_offset, idx_buffer);
}