+unsigned
+iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
+{
+ if (res->surf.dim == ISL_SURF_DIM_3D)
+ return minify(res->surf.logical_level0_px.depth, level);
+ else
+ return res->surf.logical_level0_px.array_len;
+}
+
+static enum isl_aux_state **
+create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
+{
+ uint32_t total_slices = 0;
+ for (uint32_t level = 0; level < res->surf.levels; level++)
+ total_slices += iris_get_num_logical_layers(res, level);
+
+ const size_t per_level_array_size =
+ res->surf.levels * sizeof(enum isl_aux_state *);
+
+ /* We're going to allocate a single chunk of data for both the per-level
+ * reference array and the arrays of aux_state. This makes cleanup
+ * significantly easier.
+ */
+ const size_t total_size =
+ per_level_array_size + total_slices * sizeof(enum isl_aux_state);
+
+ void *data = malloc(total_size);
+ if (!data)
+ return NULL;
+
+ enum isl_aux_state **per_level_arr = data;
+ enum isl_aux_state *s = data + per_level_array_size;
+ for (uint32_t level = 0; level < res->surf.levels; level++) {
+ per_level_arr[level] = s;
+ const unsigned level_layers = iris_get_num_logical_layers(res, level);
+ for (uint32_t a = 0; a < level_layers; a++)
+ *(s++) = initial;
+ }
+ assert((void *)s == data + total_size);
+
+ return per_level_arr;
+}
+
+/**
+ * Allocate the initial aux surface for a resource based on aux.usage
+ */
+static bool
+iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res)
+{
+ struct isl_device *isl_dev = &screen->isl_dev;
+ enum isl_aux_state initial_state;
+ UNUSED bool ok = false;
+ uint8_t memset_value = 0;
+ uint32_t alloc_flags = 0;
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ const unsigned clear_color_state_size = devinfo->gen >= 10 ?
+ screen->isl_dev.ss.clear_color_state_size :
+ (devinfo->gen >= 9 ? screen->isl_dev.ss.clear_value_size : 0);
+
+ assert(!res->aux.bo);
+
+ switch (res->aux.usage) {
+ case ISL_AUX_USAGE_NONE:
+ res->aux.surf.size_B = 0;
+ break;
+ case ISL_AUX_USAGE_HIZ:
+ initial_state = ISL_AUX_STATE_AUX_INVALID;
+ memset_value = 0;
+ ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf);
+ break;
+ case ISL_AUX_USAGE_MCS:
+ /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
+ *
+ * "When MCS buffer is enabled and bound to MSRT, it is required
+ * that it is cleared prior to any rendering."
+ *
+ * Since we only use the MCS buffer for rendering, we just clear it
+ * immediately on allocation. The clear value for MCS buffers is all
+ * 1's, so we simply memset it to 0xff.
+ */
+ initial_state = ISL_AUX_STATE_CLEAR;
+ memset_value = 0xFF;
+ ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf);
+ break;
+ case ISL_AUX_USAGE_CCS_D:
+ case ISL_AUX_USAGE_CCS_E:
+ /* When CCS_E is used, we need to ensure that the CCS starts off in
+ * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
+ * Target(s)":
+ *
+ * "If Software wants to enable Color Compression without Fast
+ * clear, Software needs to initialize MCS with zeros."
+ *
+ * A CCS value of 0 indicates that the corresponding block is in the
+ * pass-through state which is what we want.
+ *
+ * For CCS_D, do the same thing. On Gen9+, this avoids having any
+ * undefined bits in the aux buffer.
+ */
+ initial_state = ISL_AUX_STATE_PASS_THROUGH;
+ alloc_flags |= BO_ALLOC_ZEROED;
+ ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0);
+ break;
+ }
+
+ /* No work is needed for a zero-sized auxiliary buffer. */
+ if (res->aux.surf.size_B == 0)
+ return true;
+
+ /* Assert that ISL gave us a valid aux surf */
+ assert(ok);
+
+ /* Create the aux_state for the auxiliary buffer. */
+ res->aux.state = create_aux_state_map(res, initial_state);
+ if (!res->aux.state)
+ return false;
+
+ uint64_t size = res->aux.surf.size_B;
+
+ /* Allocate space in the buffer for storing the clear color. On modern
+ * platforms (gen > 9), we can read it directly from such buffer.
+ *
+ * On gen <= 9, we are going to store the clear color on the buffer
+ * anyways, and copy it back to the surface state during state emission.
+ */
+ res->aux.clear_color_offset = size;
+ size += clear_color_state_size;
+
+ /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
+ * the drm allocator. Therefore, one can pass the ISL dimensions in terms
+ * of bytes instead of trying to recalculate based on different format
+ * block sizes.
+ */
+ res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size,
+ IRIS_MEMZONE_OTHER, I915_TILING_Y,
+ res->aux.surf.row_pitch_B, alloc_flags);
+ if (!res->aux.bo) {
+ return false;
+ }
+
+ if (!(alloc_flags & BO_ALLOC_ZEROED)) {
+ void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
+
+ if (!map) {
+ iris_resource_disable_aux(res);
+ return false;
+ }
+
+ if (memset_value != 0)
+ memset(map, memset_value, res->aux.surf.size_B);
+
+ /* Zero the indirect clear color to match ::fast_clear_color. */
+ memset((char *)map + res->aux.clear_color_offset, 0,
+ clear_color_state_size);
+
+ iris_bo_unmap(res->aux.bo);
+ }
+
+ if (clear_color_state_size > 0) {
+ res->aux.clear_color_bo = res->aux.bo;
+ iris_bo_reference(res->aux.clear_color_bo);
+ }
+
+ if (res->aux.usage == ISL_AUX_USAGE_HIZ) {
+ for (unsigned level = 0; level < res->surf.levels; ++level) {
+ uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
+ uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
+
+ /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
+ * For LOD == 0, we can grow the dimensions to make it work.
+ */
+ if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
+ res->aux.has_hiz |= 1 << level;
+ }
+ }
+
+ return true;
+}
+
+static bool
+supports_mcs(const struct isl_surf *surf)
+{
+ /* MCS compression only applies to multisampled resources. */
+ if (surf->samples <= 1)
+ return false;
+
+ /* See isl_surf_get_mcs_surf for details. */
+ if (surf->samples == 16 && surf->logical_level0_px.width > 8192)
+ return false;
+
+ /* Depth and stencil buffers use the IMS (interleaved) layout. */
+ if (isl_surf_usage_is_depth_or_stencil(surf->usage))
+ return false;
+
+ return true;
+}
+
+static bool
+supports_ccs(const struct gen_device_info *devinfo,
+ const struct isl_surf *surf)
+{
+ /* Gen9+ only supports CCS for Y-tiled buffers. */
+ if (surf->tiling != ISL_TILING_Y0)
+ return false;
+
+ /* CCS only supports singlesampled resources. */
+ if (surf->samples > 1)
+ return false;
+
+ /* The PRM doesn't say this explicitly, but fast-clears don't appear to
+ * work for 3D textures until Gen9 where the layout of 3D textures changes
+ * to match 2D array textures.
+ */
+ if (devinfo->gen < 9 && surf->dim != ISL_SURF_DIM_2D)
+ return false;
+
+ /* Note: still need to check the format! */
+
+ return true;
+}
+
+static struct pipe_resource *
+iris_resource_create_for_buffer(struct pipe_screen *pscreen,
+ const struct pipe_resource *templ)
+{
+ struct iris_screen *screen = (struct iris_screen *)pscreen;
+ struct iris_resource *res = iris_alloc_resource(pscreen, templ);
+
+ assert(templ->target == PIPE_BUFFER);
+ assert(templ->height0 <= 1);
+ assert(templ->depth0 <= 1);
+ assert(templ->format == PIPE_FORMAT_NONE ||
+ util_format_get_blocksize(templ->format) == 1);
+
+ res->internal_format = templ->format;
+ res->surf.tiling = ISL_TILING_LINEAR;
+
+ enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
+ const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
+ if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
+ memzone = IRIS_MEMZONE_SHADER;
+ name = "shader kernels";
+ } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
+ memzone = IRIS_MEMZONE_SURFACE;
+ name = "surface state";
+ } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
+ memzone = IRIS_MEMZONE_DYNAMIC;
+ name = "dynamic state";
+ }
+
+ res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
+ if (!res->bo) {
+ iris_resource_destroy(pscreen, &res->base);
+ return NULL;
+ }
+
+ return &res->base;
+}
+