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gallium: add interface and state tracker support for GL_AMD_pinned_memory
[mesa.git]
/
src
/
gallium
/
drivers
/
nouveau
/
nvc0
/
nvc0_screen.c
diff --git
a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 88fc9264829f2786a9afd85f5eb896f33ba41670..edea845ecba8f279f187c22b38fb1af8ebe66dd0 100644
(file)
--- a/
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@
-171,6
+171,9
@@
nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
+ case PIPE_CAP_CLIP_HALFZ:
+ case PIPE_CAP_POLYGON_OFFSET_CLAMP:
+ case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
@@
-188,7
+191,8
@@
nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
- case PIPE_CAP_CLIP_HALFZ:
+ case PIPE_CAP_VERTEXID_NOBASE:
+ case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return 0;
case PIPE_CAP_VENDOR_ID:
return 0;
case PIPE_CAP_VENDOR_ID:
@@
-406,8
+410,6
@@
nvc0_screen_destroy(struct pipe_screen *pscreen)
FREE(screen->tic.entries);
FREE(screen->tic.entries);
- nouveau_mm_destroy(screen->mm_VRAM_fe0);
-
nouveau_object_del(&screen->eng3d);
nouveau_object_del(&screen->eng2d);
nouveau_object_del(&screen->m2mf);
nouveau_object_del(&screen->eng3d);
nouveau_object_del(&screen->eng2d);
nouveau_object_del(&screen->m2mf);
@@
-476,8
+478,8
@@
nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
PUSH_DATA (push, 0xe);
BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
PUSH_DATA (push, 0xe);
- BEGIN_NVC0(push,
SUBC_3D(0x164c
), 1);
- PUSH_DATA (push,
1 << 12
);
+ BEGIN_NVC0(push,
NVC0_3D(VERTEX_ID_GEN_MODE
), 1);
+ PUSH_DATA (push,
NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START
);
BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
@@
-601,7
+603,6
@@
nvc0_screen_create(struct nouveau_device *dev)
uint32_t obj_class;
int ret;
unsigned i;
uint32_t obj_class;
int ret;
unsigned i;
- union nouveau_bo_config mm_config;
switch (dev->chipset & ~0xf) {
case 0xc0:
switch (dev->chipset & ~0xf) {
case 0xc0:
@@
-698,10
+699,10
@@
nvc0_screen_create(struct nouveau_device *dev)
BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen->eng2d->oclass);
BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen->eng2d->oclass);
- BEGIN_NVC0(push,
NVC0_2D(
SINGLE_GPC), 1);
+ BEGIN_NVC0(push,
SUBC_2D(NVC0_2D_
SINGLE_GPC), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
- PUSH_DATA (push, NV
C
0_2D_OPERATION_SRCCOPY);
+ PUSH_DATA (push, NV
5
0_2D_OPERATION_SRCCOPY);
BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
@@
-711,7
+712,7
@@
nvc0_screen_create(struct nouveau_device *dev)
BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
PUSH_DATA (push, 1);
BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
PUSH_DATA (push, 1);
BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
- PUSH_DATA (push, NV
C
0_2D_COND_MODE_ALWAYS);
+ PUSH_DATA (push, NV
5
0_2D_COND_MODE_ALWAYS);
BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->fence.bo->offset + 16);
BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen->fence.bo->offset + 16);
@@
-789,8
+790,6
@@
nvc0_screen_create(struct nouveau_device *dev)
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
PUSH_DATA (push, 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
PUSH_DATA (push, 1);
- BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
- PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
PUSH_DATA (push, 1);
BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
PUSH_DATA (push, 1);
BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
@@
-1014,10
+1013,6
@@
nvc0_screen_create(struct nouveau_device *dev)
screen->tic.entries = CALLOC(4096, sizeof(void *));
screen->tsc.entries = screen->tic.entries + 2048;
screen->tic.entries = CALLOC(4096, sizeof(void *));
screen->tsc.entries = screen->tic.entries + 2048;
- mm_config.nvc0.tile_mode = 0;
- mm_config.nvc0.memtype = 0xfe0;
- screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
-
if (!nvc0_blitter_create(screen))
goto fail;
if (!nvc0_blitter_create(screen))
goto fail;