- struct nouveau_grobj *tesla = nv50->screen->tesla;
- struct nouveau_stateobj *so = so_new(32, 79, 18);
- struct pipe_framebuffer_state *fb = &nv50->framebuffer;
- unsigned i, w = 0, h = 0, gw = 0;
-
- /* Set nr of active RTs and select RT for each colour output.
- * FP result 0 always goes to RT[0], bits 4 - 6 are ignored.
- * Ambiguous assignment results in no rendering (no DATA_ERROR).
- */
- so_method(so, tesla, NV50TCL_RT_CONTROL, 1);
- so_data (so, fb->nr_cbufs |
- (0 << 4) | (1 << 7) | (2 << 10) | (3 << 13) |
- (4 << 16) | (5 << 19) | (6 << 22) | (7 << 25));
-
- for (i = 0; i < fb->nr_cbufs; i++) {
- struct pipe_resource *pt = fb->cbufs[i]->texture;
- struct nouveau_bo *bo = nv50_miptree(pt)->base.bo;
-
- if (!gw) {
- w = fb->cbufs[i]->width;
- h = fb->cbufs[i]->height;
- gw = 1;
- } else {
- assert(w == fb->cbufs[i]->width);
- assert(h == fb->cbufs[i]->height);
- }
-
- so_method(so, tesla, NV50TCL_RT_HORIZ(i), 2);
- so_data (so, fb->cbufs[i]->width);
- so_data (so, fb->cbufs[i]->height);
-
- so_method(so, tesla, NV50TCL_RT_ADDRESS_HIGH(i), 5);
- so_reloc (so, bo, fb->cbufs[i]->offset, NOUVEAU_BO_VRAM |
- NOUVEAU_BO_HIGH | NOUVEAU_BO_RDWR, 0, 0);
- so_reloc (so, bo, fb->cbufs[i]->offset, NOUVEAU_BO_VRAM |
- NOUVEAU_BO_LOW | NOUVEAU_BO_RDWR, 0, 0);
- switch (fb->cbufs[i]->format) {
- case PIPE_FORMAT_B8G8R8A8_UNORM:
- so_data(so, NV50TCL_RT_FORMAT_A8R8G8B8_UNORM);
- break;
- case PIPE_FORMAT_B8G8R8X8_UNORM:
- so_data(so, NV50TCL_RT_FORMAT_X8R8G8B8_UNORM);
- break;
- case PIPE_FORMAT_B5G6R5_UNORM:
- so_data(so, NV50TCL_RT_FORMAT_R5G6B5_UNORM);
- break;
- case PIPE_FORMAT_R16G16B16A16_SNORM:
- so_data(so, NV50TCL_RT_FORMAT_R16G16B16A16_SNORM);
- break;
- case PIPE_FORMAT_R16G16B16A16_UNORM:
- so_data(so, NV50TCL_RT_FORMAT_R16G16B16A16_UNORM);
- break;
- case PIPE_FORMAT_R32G32B32A32_FLOAT:
- so_data(so, NV50TCL_RT_FORMAT_R32G32B32A32_FLOAT);
- break;
- case PIPE_FORMAT_R16G16_SNORM:
- so_data(so, NV50TCL_RT_FORMAT_R16G16_SNORM);
- break;
- case PIPE_FORMAT_R16G16_UNORM:
- so_data(so, NV50TCL_RT_FORMAT_R16G16_UNORM);
- break;
- default:
- NOUVEAU_ERR("AIIII unknown format %s\n",
- util_format_name(fb->cbufs[i]->format));
- so_data(so, NV50TCL_RT_FORMAT_X8R8G8B8_UNORM);
- break;
- }
- so_data(so, nv50_miptree(pt)->
- level[fb->cbufs[i]->level].tile_mode << 4);
- so_data(so, 0x00000000);
-
- so_method(so, tesla, NV50TCL_RT_ARRAY_MODE, 1);
- so_data (so, 1);
- }
-
- if (fb->zsbuf) {
- struct pipe_resource *pt = fb->zsbuf->texture;
- struct nouveau_bo *bo = nv50_miptree(pt)->base.bo;
-
- if (!gw) {
- w = fb->zsbuf->width;
- h = fb->zsbuf->height;
- gw = 1;
- } else {
- assert(w == fb->zsbuf->width);
- assert(h == fb->zsbuf->height);
- }
-
- so_method(so, tesla, NV50TCL_ZETA_ADDRESS_HIGH, 5);
- so_reloc (so, bo, fb->zsbuf->offset, NOUVEAU_BO_VRAM |
- NOUVEAU_BO_HIGH | NOUVEAU_BO_RDWR, 0, 0);
- so_reloc (so, bo, fb->zsbuf->offset, NOUVEAU_BO_VRAM |
- NOUVEAU_BO_LOW | NOUVEAU_BO_RDWR, 0, 0);
- switch (fb->zsbuf->format) {
- case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
- so_data(so, NV50TCL_ZETA_FORMAT_S8Z24_UNORM);
- break;
- case PIPE_FORMAT_Z24X8_UNORM:
- so_data(so, NV50TCL_ZETA_FORMAT_X8Z24_UNORM);
- break;
- case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
- so_data(so, NV50TCL_ZETA_FORMAT_Z24S8_UNORM);
- break;
- case PIPE_FORMAT_Z32_FLOAT:
- so_data(so, NV50TCL_ZETA_FORMAT_Z32_FLOAT);
- break;
- default:
- NOUVEAU_ERR("AIIII unknown format %s\n",
- util_format_name(fb->zsbuf->format));
- so_data(so, NV50TCL_ZETA_FORMAT_S8Z24_UNORM);
- break;
- }
- so_data(so, nv50_miptree(pt)->
- level[fb->zsbuf->level].tile_mode << 4);
- so_data(so, 0x00000000);
-
- so_method(so, tesla, NV50TCL_ZETA_ENABLE, 1);
- so_data (so, 1);
- so_method(so, tesla, NV50TCL_ZETA_HORIZ, 3);
- so_data (so, fb->zsbuf->width);
- so_data (so, fb->zsbuf->height);
- so_data (so, 0x00010001);
- } else {
- so_method(so, tesla, NV50TCL_ZETA_ENABLE, 1);
- so_data (so, 0);
- }
-
- so_method(so, tesla, NV50TCL_VIEWPORT_HORIZ(0), 2);
- so_data (so, w << 16);
- so_data (so, h << 16);
- /* set window lower left corner */
- so_method(so, tesla, NV50TCL_WINDOW_OFFSET_X, 2);
- so_data (so, 0);
- so_data (so, 0);
- /* set screen scissor rectangle */
- so_method(so, tesla, NV50TCL_SCREEN_SCISSOR_HORIZ, 2);
- so_data (so, w << 16);
- so_data (so, h << 16);
-
- return so;
+ struct nouveau_channel *chan = nv50->screen->base.channel;
+ struct pipe_framebuffer_state *fb = &nv50->framebuffer;
+ unsigned i;
+ unsigned ms_mode = NV50_3D_MULTISAMPLE_MODE_MS1;
+ boolean serialize = FALSE;
+
+ nv50_bufctx_reset(nv50, NV50_BUFCTX_FRAME);
+
+ BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
+ OUT_RING (chan, (076543210 << 4) | fb->nr_cbufs);
+ BEGIN_RING(chan, RING_3D(SCREEN_SCISSOR_HORIZ), 2);
+ OUT_RING (chan, fb->width << 16);
+ OUT_RING (chan, fb->height << 16);
+
+ MARK_RING(chan, 9 * fb->nr_cbufs, 2 * fb->nr_cbufs);
+
+ for (i = 0; i < fb->nr_cbufs; ++i) {
+ struct nv50_miptree *mt = nv50_miptree(fb->cbufs[i]->texture);
+ struct nv50_surface *sf = nv50_surface(fb->cbufs[i]);
+ struct nouveau_bo *bo = mt->base.bo;
+ uint32_t offset = sf->offset;
+
+ BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 5);
+ OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+ OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+ OUT_RING (chan, nv50_format_table[sf->base.format].rt);
+ OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode << 4);
+ OUT_RING (chan, mt->layer_stride >> 2);
+ BEGIN_RING(chan, RING_3D(RT_HORIZ(i)), 2);
+ OUT_RING (chan, sf->width);
+ OUT_RING (chan, sf->height);
+ BEGIN_RING(chan, RING_3D(RT_ARRAY_MODE), 1);
+ OUT_RING (chan, sf->depth);
+
+ ms_mode = mt->ms_mode;
+
+ if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
+ serialize = TRUE;
+ mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
+
+ /* only register for writing, otherwise we'd always serialize here */
+ nv50_bufctx_add_resident(nv50, NV50_BUFCTX_FRAME, &mt->base,
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ }
+
+ if (fb->zsbuf) {
+ struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
+ struct nv50_surface *sf = nv50_surface(fb->zsbuf);
+ struct nouveau_bo *bo = mt->base.bo;
+ int unk = mt->base.base.target == PIPE_TEXTURE_2D;
+ uint32_t offset = sf->offset;
+
+ MARK_RING (chan, 12, 2);
+ BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
+ OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+ OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+ OUT_RING (chan, nv50_format_table[fb->zsbuf->format].rt);
+ OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode << 4);
+ OUT_RING (chan, mt->layer_stride >> 2);
+ BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
+ OUT_RING (chan, 1);
+ BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
+ OUT_RING (chan, sf->width);
+ OUT_RING (chan, sf->height);
+ OUT_RING (chan, (unk << 16) | sf->depth);
+
+ ms_mode = mt->ms_mode;
+
+ if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
+ serialize = TRUE;
+ mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
+
+ nv50_bufctx_add_resident(nv50, NV50_BUFCTX_FRAME, &mt->base,
+ NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+ } else {
+ BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
+ OUT_RING (chan, 0);
+ }
+
+ BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
+ OUT_RING (chan, ms_mode);
+
+ BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
+ OUT_RING (chan, fb->width << 16);
+ OUT_RING (chan, fb->height << 16);
+
+ if (serialize) {
+ BEGIN_RING(chan, RING_3D(SERIALIZE), 1);
+ OUT_RING (chan, 0);
+ }