- uint32_t offset = sf->offset;
-
- BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 5);
- OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
- OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
- OUT_RING (chan, nv50_format_table[sf->base.format].rt);
- OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode << 4);
- OUT_RING (chan, mt->layer_stride >> 2);
- BEGIN_RING(chan, RING_3D(RT_HORIZ(i)), 2);
- OUT_RING (chan, sf->width);
- OUT_RING (chan, sf->height);
- BEGIN_RING(chan, RING_3D(RT_ARRAY_MODE), 1);
- OUT_RING (chan, sf->depth);
-
- nv50_bufctx_add_resident(nv50, NV50_BUFCTX_FRAME, &mt->base,
- NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+
+ BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
+ PUSH_DATAh(push, bo->offset + sf->offset);
+ PUSH_DATA (push, bo->offset + sf->offset);
+ PUSH_DATA (push, nv50_format_table[sf->base.format].rt);
+ if (likely(nouveau_bo_memtype(bo))) {
+ PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
+ PUSH_DATA (push, mt->layer_stride >> 2);
+ BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
+ PUSH_DATA (push, sf->width);
+ PUSH_DATA (push, sf->height);
+ BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
+ PUSH_DATA (push, sf->depth);
+ } else {
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 0);
+ BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
+ PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
+ PUSH_DATA (push, sf->height);
+ BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
+ PUSH_DATA (push, 0);
+
+ assert(!fb->zsbuf);
+ assert(!mt->ms_mode);
+ }
+
+ ms_mode = mt->ms_mode;
+
+ if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
+ nv50->state.rt_serialize = TRUE;
+ mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
+
+ /* only register for writing, otherwise we'd always serialize here */
+ BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR);