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Merge remote branch 'origin/nv50-compiler'
[mesa.git]
/
src
/
gallium
/
drivers
/
r300
/
r300_chipset.c
diff --git
a/src/gallium/drivers/r300/r300_chipset.c
b/src/gallium/drivers/r300/r300_chipset.c
index 00fae8d26f3df80d1efede5f938a2baf314be5a8..48c24092114013332c04e5134ca2ec3120989b8e 100644
(file)
--- a/
src/gallium/drivers/r300/r300_chipset.c
+++ b/
src/gallium/drivers/r300/r300_chipset.c
@@
-21,8
+21,11
@@
* USE OR OTHER DEALINGS IN THE SOFTWARE. */
#include "r300_chipset.h"
* USE OR OTHER DEALINGS IN THE SOFTWARE. */
#include "r300_chipset.h"
+
#include "util/u_debug.h"
#include "util/u_debug.h"
+#include <stdio.h>
+
/* r300_chipset: A file all to itself for deducing the various properties of
* Radeons. */
/* r300_chipset: A file all to itself for deducing the various properties of
* Radeons. */
@@
-30,9
+33,13
@@
void r300_parse_chipset(struct r300_capabilities* caps)
{
/* Reasonable defaults */
void r300_parse_chipset(struct r300_capabilities* caps)
{
/* Reasonable defaults */
- caps->has_tcl = getenv("RADEON_NO_TCL") ? FALSE : TRUE;
+ caps->num_vert_fpus = 2;
+ caps->num_tex_units = 16;
+ caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
+ caps->hiz_ram = 0;
+ caps->is_r400 = FALSE;
caps->is_r500 = FALSE;
caps->is_r500 = FALSE;
- caps->
num_vert_fpus = 4
;
+ caps->
high_second_pipe = FALSE
;
/* Note: These are not ordered by PCI ID. I leave that task to GCC,
* which will perform the ordering while collating jump tables. Instead,
/* Note: These are not ordered by PCI ID. I leave that task to GCC,
* which will perform the ordering while collating jump tables. Instead,
@@
-40,6
+47,10
@@
void r300_parse_chipset(struct r300_capabilities* caps)
switch (caps->pci_id) {
case 0x4144:
caps->family = CHIP_FAMILY_R300;
switch (caps->pci_id) {
case 0x4144:
caps->family = CHIP_FAMILY_R300;
+ caps->high_second_pipe = TRUE;
+ caps->num_vert_fpus = 4;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x4145:
break;
case 0x4145:
@@
-50,6
+61,10
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x4E46:
case 0x4E47:
caps->family = CHIP_FAMILY_R300;
case 0x4E46:
case 0x4E47:
caps->family = CHIP_FAMILY_R300;
+ caps->high_second_pipe = TRUE;
+ caps->num_vert_fpus = 4;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x4150:
break;
case 0x4150:
@@
-66,6
+81,8
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x4E54:
case 0x4E56:
caps->family = CHIP_FAMILY_RV350;
case 0x4E54:
case 0x4E56:
caps->family = CHIP_FAMILY_RV350;
+ caps->high_second_pipe = TRUE;
+ caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
case 0x4148:
break;
case 0x4148:
@@
-76,10
+93,18
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x4E49:
case 0x4E4B:
caps->family = CHIP_FAMILY_R350;
case 0x4E49:
case 0x4E4B:
caps->family = CHIP_FAMILY_R350;
+ caps->high_second_pipe = TRUE;
+ caps->num_vert_fpus = 4;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x4E4A:
caps->family = CHIP_FAMILY_R360;
break;
case 0x4E4A:
caps->family = CHIP_FAMILY_R360;
+ caps->high_second_pipe = TRUE;
+ caps->num_vert_fpus = 4;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x5460:
break;
case 0x5460:
@@
-91,14
+116,20
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x5B64:
case 0x5B65:
caps->family = CHIP_FAMILY_RV370;
case 0x5B64:
case 0x5B65:
caps->family = CHIP_FAMILY_RV370;
+ caps->high_second_pipe = TRUE;
+ caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
case 0x3150:
case 0x3152:
case 0x3154:
break;
case 0x3150:
case 0x3152:
case 0x3154:
+ case 0x3155:
case 0x3E50:
case 0x3E54:
caps->family = CHIP_FAMILY_RV380;
case 0x3E50:
case 0x3E54:
caps->family = CHIP_FAMILY_RV380;
+ caps->high_second_pipe = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
case 0x4A48:
break;
case 0x4A48:
@@
-113,6
+144,9
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x4A54:
caps->family = CHIP_FAMILY_R420;
caps->num_vert_fpus = 6;
case 0x4A54:
caps->family = CHIP_FAMILY_R420;
caps->num_vert_fpus = 6;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x5548:
break;
case 0x5548:
@@
-126,6
+160,9
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x5D57:
caps->family = CHIP_FAMILY_R423;
caps->num_vert_fpus = 6;
case 0x5D57:
caps->family = CHIP_FAMILY_R423;
caps->num_vert_fpus = 6;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x554C:
break;
case 0x554C:
@@
-137,6
+174,9
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x5D4A:
caps->family = CHIP_FAMILY_R430;
caps->num_vert_fpus = 6;
case 0x5D4A:
caps->family = CHIP_FAMILY_R430;
caps->num_vert_fpus = 6;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x5D4C:
break;
case 0x5D4C:
@@
-147,6
+187,9
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x5D52:
caps->family = CHIP_FAMILY_R480;
caps->num_vert_fpus = 6;
case 0x5D52:
caps->family = CHIP_FAMILY_R480;
caps->num_vert_fpus = 6;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x4B48:
break;
case 0x4B48:
@@
-156,6
+199,9
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x4B4C:
caps->family = CHIP_FAMILY_R481;
caps->num_vert_fpus = 6;
case 0x4B4C:
caps->family = CHIP_FAMILY_R481;
caps->num_vert_fpus = 6;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x5E4C:
break;
case 0x5E4C:
@@
-172,36
+218,46
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x5E4D:
caps->family = CHIP_FAMILY_RV410;
caps->num_vert_fpus = 6;
case 0x5E4D:
caps->family = CHIP_FAMILY_RV410;
caps->num_vert_fpus = 6;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x5954:
case 0x5955:
caps->family = CHIP_FAMILY_RS480;
caps->has_tcl = FALSE;
break;
case 0x5954:
case 0x5955:
caps->family = CHIP_FAMILY_RS480;
caps->has_tcl = FALSE;
+ caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
case 0x5974:
case 0x5975:
caps->family = CHIP_FAMILY_RS482;
caps->has_tcl = FALSE;
break;
case 0x5974:
case 0x5975:
caps->family = CHIP_FAMILY_RS482;
caps->has_tcl = FALSE;
+ caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
case 0x5A41:
case 0x5A42:
caps->family = CHIP_FAMILY_RS400;
caps->has_tcl = FALSE;
break;
case 0x5A41:
case 0x5A42:
caps->family = CHIP_FAMILY_RS400;
caps->has_tcl = FALSE;
+ caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
case 0x5A61:
case 0x5A62:
caps->family = CHIP_FAMILY_RC410;
caps->has_tcl = FALSE;
break;
case 0x5A61:
case 0x5A62:
caps->family = CHIP_FAMILY_RC410;
caps->has_tcl = FALSE;
+ caps->zmask_ram = RV3xx_ZMASK_SIZE;
break;
case 0x791E:
case 0x791F:
caps->family = CHIP_FAMILY_RS690;
caps->has_tcl = FALSE;
break;
case 0x791E:
case 0x791F:
caps->family = CHIP_FAMILY_RS690;
caps->has_tcl = FALSE;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x793F:
break;
case 0x793F:
@@
-209,6
+265,9
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x7942:
caps->family = CHIP_FAMILY_RS600;
caps->has_tcl = FALSE;
case 0x7942:
caps->family = CHIP_FAMILY_RS600;
caps->has_tcl = FALSE;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x796C:
break;
case 0x796C:
@@
-217,6
+276,9
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x796F:
caps->family = CHIP_FAMILY_RS740;
caps->has_tcl = FALSE;
case 0x796F:
caps->family = CHIP_FAMILY_RS740;
caps->has_tcl = FALSE;
+ caps->is_r400 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x7100:
break;
case 0x7100:
@@
-236,6
+298,8
@@
void r300_parse_chipset(struct r300_capabilities* caps)
caps->family = CHIP_FAMILY_R520;
caps->num_vert_fpus = 8;
caps->is_r500 = TRUE;
caps->family = CHIP_FAMILY_R520;
caps->num_vert_fpus = 8;
caps->is_r500 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x7140:
break;
case 0x7140:
@@
-279,6
+343,8
@@
void r300_parse_chipset(struct r300_capabilities* caps)
caps->family = CHIP_FAMILY_RV515;
caps->num_vert_fpus = 2;
caps->is_r500 = TRUE;
caps->family = CHIP_FAMILY_RV515;
caps->num_vert_fpus = 2;
caps->is_r500 = TRUE;
+ caps->hiz_ram = R300_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x71C0:
break;
case 0x71C0:
@@
-300,6
+366,8
@@
void r300_parse_chipset(struct r300_capabilities* caps)
caps->family = CHIP_FAMILY_RV530;
caps->num_vert_fpus = 5;
caps->is_r500 = TRUE;
caps->family = CHIP_FAMILY_RV530;
caps->num_vert_fpus = 5;
caps->is_r500 = TRUE;
+ /*caps->hiz_ram = RV530_HIZ_LIMIT;*/
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x7240:
break;
case 0x7240:
@@
-320,12
+388,16
@@
void r300_parse_chipset(struct r300_capabilities* caps)
caps->family = CHIP_FAMILY_R580;
caps->num_vert_fpus = 8;
caps->is_r500 = TRUE;
caps->family = CHIP_FAMILY_R580;
caps->num_vert_fpus = 8;
caps->is_r500 = TRUE;
+ caps->hiz_ram = RV530_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x7280:
caps->family = CHIP_FAMILY_RV570;
break;
case 0x7280:
caps->family = CHIP_FAMILY_RV570;
- caps->num_vert_fpus =
5
;
+ caps->num_vert_fpus =
8
;
caps->is_r500 = TRUE;
caps->is_r500 = TRUE;
+ caps->hiz_ram = RV530_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
case 0x7281:
break;
case 0x7281:
@@
-340,13
+412,16
@@
void r300_parse_chipset(struct r300_capabilities* caps)
case 0x7293:
case 0x7297:
caps->family = CHIP_FAMILY_RV560;
case 0x7293:
case 0x7297:
caps->family = CHIP_FAMILY_RV560;
- caps->num_vert_fpus =
5
;
+ caps->num_vert_fpus =
8
;
caps->is_r500 = TRUE;
caps->is_r500 = TRUE;
+ caps->hiz_ram = RV530_HIZ_LIMIT;
+ caps->zmask_ram = PIPE_ZMASK_SIZE;
break;
default:
break;
default:
- debug_printf("r300: Warning: Unknown chipset 0x%x\n",
- caps->pci_id);
- break;
+ fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\n",
+ caps->pci_id);
}
}
+
+ caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350;
}
}