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[g3dvl] move z-coord generation for multiple render targets into vertex shader
[mesa.git]
/
src
/
gallium
/
drivers
/
r300
/
r300_chipset.h
diff --git
a/src/gallium/drivers/r300/r300_chipset.h
b/src/gallium/drivers/r300/r300_chipset.h
index ab649c385730b14eb403a8488a09b87e44d26cf0..e7ca642b4f3e4876901410018cc7e6bbdd99847f 100644
(file)
--- a/
src/gallium/drivers/r300/r300_chipset.h
+++ b/
src/gallium/drivers/r300/r300_chipset.h
@@
-25,6
+25,14
@@
#include "pipe/p_compiler.h"
#include "pipe/p_compiler.h"
+/* these are sizes in dwords */
+#define R300_HIZ_LIMIT 10240
+#define RV530_HIZ_LIMIT 15360
+
+/* rv3xx have only one pipe */
+#define PIPE_ZMASK_SIZE 4096
+#define RV3xx_ZMASK_SIZE 5120
+
/* Structure containing all the possible information about a specific Radeon
* in the R3xx, R4xx, and R5xx families. */
struct r300_capabilities {
/* Structure containing all the possible information about a specific Radeon
* in the R3xx, R4xx, and R5xx families. */
struct r300_capabilities {
@@
-42,6
+50,10
@@
struct r300_capabilities {
unsigned num_tex_units;
/* Whether or not TCL is physically present */
boolean has_tcl;
unsigned num_tex_units;
/* Whether or not TCL is physically present */
boolean has_tcl;
+ /* Some chipsets do not have HiZ RAM - other have varying amounts . */
+ int hiz_ram;
+ /* some chipsets have zmask ram per pipe some don't */
+ int zmask_ram;
/* Whether or not this is RV350 or newer, including all r400 and r500
* chipsets. The differences compared to the oldest r300 chips are:
* - Blend LTE/GTE thresholds
/* Whether or not this is RV350 or newer, including all r400 and r500
* chipsets. The differences compared to the oldest r300 chips are:
* - Blend LTE/GTE thresholds