+ r300_emit_hyperz_end(r300);
+ r300_emit_query_end(r300);
+ if (r300->screen->caps.is_r500)
+ r500_emit_index_bias(r300, 0);
+
+ /* The DDX doesn't set these regs. */
+ if (r300->screen->info.drm_minor >= 6) {
+ CS_LOCALS(r300);
+ OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
+ OUT_CS(0x66666666);
+ OUT_CS(0x6666666);
+ }
+
+ r300->flush_counter++;
+ r300->rws->cs_flush(r300->cs, flags, 0);
+ r300->dirty_hw = 0;
+
+ /* New kitchen sink, baby. */
+ foreach_atom(r300, atom) {
+ if (atom->state || atom->allow_null_state) {
+ r300_mark_atom_dirty(r300, atom);
+ }
+ }
+ r300->vertex_arrays_dirty = TRUE;
+
+ /* Unmark HWTCL state for SWTCL. */
+ if (!r300->screen->caps.has_tcl) {
+ r300->vs_state.dirty = FALSE;
+ r300->vs_constants.dirty = FALSE;
+ r300->clip_state.dirty = FALSE;
+ }
+}
+
+void r300_flush(struct pipe_context *pipe,
+ unsigned flags,
+ struct pipe_fence_handle **fence)
+{
+ struct r300_context *r300 = r300_context(pipe);
+ struct pb_buffer **rfence = (struct pb_buffer**)fence;
+
+ if (r300->screen->info.drm_minor >= 12) {
+ flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+ }