-#if 0
- BEGIN_CS();
- OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT,(RADEON_DEFAULT_SC_RIGHT_MAX |
- RADEON_DEFAULT_SC_BOTTOM_MAX));
- OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
- RADEON_GMC_BRUSH_NONE |
- (datatype << 8) |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- RADEON_ROP[rop].rop |
- RADEON_DP_SRC_SOURCE_MEMORY |
- RADEON_GMC_CLR_CMP_CNTL_DIS));
- OUT_CS_REG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
- OUT_CS_REG(RADEON_DP_BRUSH_BKGD_CLR, 0x0);
- OUT_CS_REG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
- OUT_CS_REG(RADEON_DP_SRC_BKGD_CLR, 0x0);
- OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask);
- OUT_ACCEL_REG(RADEON_DP_CNTL, ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
- (info->accel_state->ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0));
-);
-
- OUT_CS_REG_SEQ(RADEON_DST_PITCH_OFFSET, 1);
- OUT_CS_RELOC(desttex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-
- OUT_CS_REG_SEQ(RADEON_SRC_PITCH_OFFSET, 1);
- OUT_CS_RELOC(srctex->buffer, 0,
- RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0, 0);
-
- OUT_CS_REG(RADEON_SRC_Y_X, (srcy << 16) | srcx);
- OUT_CS_REG(RADEON_DST_Y_X, (desty << 16) | destx);
- OUT_CS_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
- OUT_CS_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
- OUT_CS_REG(RADEON_WAIT_UNTIL,
- RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
+
+ /* Add our target BOs to the list. */
+validate:
+ if (!r300->winsys->add_buffer(r300->winsys, srctex->buffer,
+ RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0)) {
+ r300->context.flush(&r300->context, 0, NULL);
+ goto validate;
+ }
+ if (!r300->winsys->add_buffer(r300->winsys, desttex->buffer,
+ 0, RADEON_GEM_DOMAIN_VRAM)) {
+ r300->context.flush(&r300->context, 0, NULL);
+ goto validate;
+ }
+ if (r300->winsys->validate(r300->winsys)) {
+ r300->context.flush(&r300->context, 0, NULL);
+ if (invalid) {
+ goto fallback;
+ }
+ invalid = TRUE;
+ goto validate;
+ }
+
+ r300_surface_setup(r300, desttex, destx, desty, w, h);
+
+ /* Setup the texture. */
+ r300_emit_sampler(r300, &r300_sampler_copy_state, 0);
+ r300_emit_texture(r300, srctex, 0);
+
+ /* Flush and enable. */
+ BEGIN_CS(4);
+ OUT_CS_REG(R300_TX_INVALTAGS, 0);
+ OUT_CS_REG(R300_TX_ENABLE, 0x1);
+ END_CS;
+
+ /* Vertex shader setup */
+ if (caps->has_tcl) {
+ r300_emit_vertex_shader(r300, &r300_passthrough_vertex_shader);
+ } else {
+ BEGIN_CS(4);
+ OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VAP_TCL_BYPASS);
+ OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(5) |
+ R300_PVS_NUM_CNTLRS(5) |
+ R300_PVS_NUM_FPUS(caps->num_vert_fpus) |
+ R300_PVS_VF_MAX_VTX_NUM(12));
+ END_CS;
+ }
+
+ /* Fragment shader setup */
+ if (caps->is_r500) {
+ r500_emit_fragment_shader(r300, &r5xx_texture_fragment_shader);
+ r300_emit_rs_block_state(r300, &r5xx_rs_block_copy_state);
+ } else {
+ r300_emit_fragment_shader(r300, &r3xx_texture_fragment_shader);
+ r300_emit_rs_block_state(r300, &r3xx_rs_block_copy_state);
+ }
+
+ BEGIN_CS(30);
+ /* VAP stream control, mapping from input memory to PVS/RS memory */
+ if (caps->has_tcl) {
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
+ R300_DATA_TYPE_FLOAT_2) << R300_DATA_TYPE_1_SHIFT));
+ } else {
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ ((R300_LAST_VEC | (6 << R300_DST_VEC_LOC_SHIFT) |
+ R300_DATA_TYPE_FLOAT_2) << R300_DATA_TYPE_1_SHIFT));
+ }
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE0_SHIFT) |
+ (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE1_SHIFT));
+
+ /* VAP format controls */
+ OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0,
+ R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT);
+ /* Two components of texture 0 */
+ OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x2);
+
+ /* Vertex size. */
+ OUT_CS_REG(R300_VAP_VTX_SIZE, 0x4);
+
+ /* Packet3 with our texcoords */
+ OUT_CS_PKT3(R200_3D_DRAW_IMMD_2, 16);
+ OUT_CS(R300_PRIM_TYPE_QUADS | R300_PRIM_WALK_RING |
+ (4 << R300_PRIM_NUM_VERTICES_SHIFT));
+ /* (x , y ) */
+ OUT_CS_32F(fdestx / dest->width);
+ OUT_CS_32F(fdesty / dest->height);
+ OUT_CS_32F(fsrcx / src->width);
+ OUT_CS_32F(fsrcy / src->height);
+ /* (x , y + h) */
+ OUT_CS_32F(fdestx / dest->width);
+ OUT_CS_32F((fdesty + h) / dest->height);
+ OUT_CS_32F(fsrcx / src->width);
+ OUT_CS_32F((fsrcy + h) / src->height);
+ /* (x + w, y + h) */
+ OUT_CS_32F((fdestx + w) / dest->width);
+ OUT_CS_32F((fdesty + h) / dest->height);
+ OUT_CS_32F((fsrcx + w) / src->width);
+ OUT_CS_32F((fsrcy + h) / src->height);
+ /* (x + w, y ) */
+ OUT_CS_32F((fdestx + w) / dest->width);
+ OUT_CS_32F(fdesty / dest->height);
+ OUT_CS_32F((fsrcx + w) / src->width);
+ OUT_CS_32F(fsrcy / src->height);
+
+ OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
+