+ if (!rctx->cmd_buf_is_compute) {
+ rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
+ rctx->cmd_buf_is_compute = true;
+ }
+
+ if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI) {
+ r600_shader_select(&rctx->b.b, rctx->cs_shader_state.shader->sel, &compute_dirty);
+ current = rctx->cs_shader_state.shader->sel->current;
+ if (compute_dirty) {
+ rctx->cs_shader_state.atom.num_dw = current->command_buffer.num_dw;
+ r600_context_add_resource_size(&rctx->b.b, (struct pipe_resource *)current->bo);
+ r600_set_atom_dirty(rctx, &rctx->cs_shader_state.atom, true);
+ }
+
+ bool need_buf_const = current->shader.uses_tex_buffers ||
+ current->shader.has_txq_cube_array_z_comp;
+
+ if (info->indirect) {
+ struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect;
+ unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource, PIPE_TRANSFER_READ);
+ unsigned offset = info->indirect_offset / 4;
+ indirect_grid[0] = data[offset];
+ indirect_grid[1] = data[offset + 1];
+ indirect_grid[2] = data[offset + 2];
+ }
+ for (int i = 0; i < 3; i++) {
+ rctx->cs_block_grid_sizes[i] = info->block[i];
+ rctx->cs_block_grid_sizes[i + 4] = info->indirect ? indirect_grid[i] : info->grid[i];
+ }
+ rctx->cs_block_grid_sizes[3] = rctx->cs_block_grid_sizes[7] = 0;
+ rctx->driver_consts[PIPE_SHADER_COMPUTE].cs_block_grid_size_dirty = true;
+
+ evergreen_emit_atomic_buffer_setup_count(rctx, current, combined_atomics, &atomic_used_mask);
+ r600_need_cs_space(rctx, 0, true, util_bitcount(atomic_used_mask));
+
+ if (need_buf_const) {
+ eg_setup_buffer_constants(rctx, PIPE_SHADER_COMPUTE);
+ }
+ r600_update_driver_const_buffers(rctx, true);
+
+ evergreen_emit_atomic_buffer_setup(rctx, true, combined_atomics, atomic_used_mask);
+ if (atomic_used_mask) {
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+ }
+ } else
+ r600_need_cs_space(rctx, 0, true, 0);
+
+ /* Initialize all the compute-related registers.
+ *
+ * See evergreen_init_atom_start_compute_cs() in this file for the list
+ * of registers initialized by the start_compute_cs_cmd atom.
+ */
+ r600_emit_command_buffer(cs, &rctx->start_compute_cs_cmd);
+
+ /* emit config state */
+ if (rctx->b.chip_class == EVERGREEN) {
+ if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI) {
+ radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
+ radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
+ radeon_emit(cs, 0);
+ radeon_emit(cs, 0);
+ radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
+ } else
+ r600_emit_atom(rctx, &rctx->config_state.atom);
+ }
+
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+ r600_flush_emit(rctx);
+
+ if (rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_TGSI) {
+
+ compute_setup_cbs(rctx);
+
+ /* Emit vertex buffer state */
+ rctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(rctx->cs_vertex_buffer_state.dirty_mask);
+ r600_emit_atom(rctx, &rctx->cs_vertex_buffer_state.atom);
+ } else {
+ uint32_t rat_mask;
+
+ rat_mask = evergreen_construct_rat_mask(rctx, &rctx->cb_misc_state, 0);
+ radeon_compute_set_context_reg(cs, R_028238_CB_TARGET_MASK,
+ rat_mask);
+ }
+
+ r600_emit_atom(rctx, &rctx->b.render_cond_atom);