+const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
+ SQ_ALU_VEC_120, //001
+ SQ_ALU_VEC_102, //010
+
+ SQ_ALU_VEC_201, //011
+ SQ_ALU_VEC_012, //100
+ SQ_ALU_VEC_021, //101
+
+ SQ_ALU_VEC_012, //110
+ SQ_ALU_VEC_012}; //111
+
+const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
+ SQ_ALU_SCL_122, //001
+ SQ_ALU_SCL_122, //010
+
+ SQ_ALU_SCL_221, //011
+ SQ_ALU_SCL_212, //100
+ SQ_ALU_SCL_122, //101
+
+ SQ_ALU_SCL_122, //110
+ SQ_ALU_SCL_122}; //111
+
+static int init_gpr(struct r600_bc_alu *alu)
+{
+ int cycle, component;
+ /* set up gpr use */
+ for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
+ for (component = 0; component < NUM_OF_COMPONENTS; component++)
+ alu->hw_gpr[cycle][component] = -1;
+ return 0;
+}
+
+#if 0
+static int reserve_gpr(struct r600_bc_alu *alu, unsigned sel, unsigned chan, unsigned cycle)
+{
+ if (alu->hw_gpr[cycle][chan] < 0)
+ alu->hw_gpr[cycle][chan] = sel;
+ else if (alu->hw_gpr[cycle][chan] != (int)sel) {
+ R600_ERR("Another scalar operation has already used GPR read port for channel\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int cycle_for_scalar_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
+{
+ int table[3];
+ int ret = 0;
+ switch (swiz) {
+ case SQ_ALU_SCL_210:
+ table[0] = 2; table[1] = 1; table[2] = 0;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_SCL_122:
+ table[0] = 1; table[1] = 2; table[2] = 2;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_SCL_212:
+ table[0] = 2; table[1] = 1; table[2] = 2;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_SCL_221:
+ table[0] = 2; table[1] = 2; table[2] = 1;
+ *p_cycle = table[sel];
+ break;
+ break;
+ default:
+ R600_ERR("bad scalar bank swizzle value\n");
+ ret = -1;
+ break;
+ }
+ return ret;
+}
+
+static int cycle_for_vector_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
+{
+ int table[3];
+ int ret;
+
+ switch (swiz) {
+ case SQ_ALU_VEC_012:
+ table[0] = 0; table[1] = 1; table[2] = 2;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_VEC_021:
+ table[0] = 0; table[1] = 2; table[2] = 1;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_VEC_120:
+ table[0] = 1; table[1] = 2; table[2] = 0;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_VEC_102:
+ table[0] = 1; table[1] = 0; table[2] = 2;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_VEC_201:
+ table[0] = 2; table[1] = 0; table[2] = 1;
+ *p_cycle = table[sel];
+ break;
+ case SQ_ALU_VEC_210:
+ table[0] = 2; table[1] = 1; table[2] = 0;
+ *p_cycle = table[sel];
+ break;
+ default:
+ R600_ERR("bad vector bank swizzle value\n");
+ ret = -1;
+ break;
+ }
+ return ret;
+}
+
+
+
+static void update_chan_counter(struct r600_bc_alu *alu, int *chan_counter)
+{
+ int num_src;
+ int i;
+ int channel_swizzle;
+
+ num_src = r600_bc_get_num_operands(alu);
+
+ for (i = 0; i < num_src; i++) {
+ channel_swizzle = alu->src[i].chan;
+ if ((alu->src[i].sel > 0 && alu->src[i].sel < 128) && channel_swizzle <= 3)
+ chan_counter[channel_swizzle]++;
+ }
+}
+
+/* we need something like this I think - but this is bogus */
+int check_read_slots(struct r600_bc *bc, struct r600_bc_alu *alu_first)
+{
+ struct r600_bc_alu *alu;
+ int chan_counter[4] = { 0 };
+
+ update_chan_counter(alu_first, chan_counter);
+
+ LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
+ update_chan_counter(alu, chan_counter);
+ }
+
+ if (chan_counter[0] > 3 ||
+ chan_counter[1] > 3 ||
+ chan_counter[2] > 3 ||
+ chan_counter[3] > 3) {
+ R600_ERR("needed to split instruction for input ran out of banks %x %d %d %d %d\n",
+ alu_first->inst, chan_counter[0], chan_counter[1], chan_counter[2], chan_counter[3]);
+ return -1;
+ }
+ return 0;
+}
+#endif
+
+static int is_const(int sel)
+{
+ if (sel > 255 && sel < 512)
+ return 1;
+ if (sel >= V_SQ_ALU_SRC_0 && sel <= V_SQ_ALU_SRC_LITERAL)
+ return 1;
+ return 0;
+}
+
+static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu)
+{
+ unsigned swizzle_key;
+
+ if (alu->bank_swizzle_force) {
+ alu->bank_swizzle = alu->bank_swizzle_force;
+ return 0;
+ }
+ swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
+ (is_const(alu->src[1].sel) ? 2 : 0 ) +
+ (is_const(alu->src[2].sel) ? 1 : 0 );
+
+ alu->bank_swizzle = bank_swizzle_scl[swizzle_key];
+ return 0;
+}
+
+static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu)
+{
+ unsigned swizzle_key;
+
+ if (alu->bank_swizzle_force) {
+ alu->bank_swizzle = alu->bank_swizzle_force;
+ return 0;
+ }
+ swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
+ (is_const(alu->src[1].sel) ? 2 : 0 ) +
+ (is_const(alu->src[2].sel) ? 1 : 0 );
+
+ alu->bank_swizzle = bank_swizzle_vec[swizzle_key];
+ return 0;
+}
+
+static int check_and_set_bank_swizzle(struct r600_bc *bc, struct r600_bc_alu *alu_first)
+{
+ struct r600_bc_alu *alu = NULL;
+ int num_instr = 1;
+
+ init_gpr(alu_first);
+
+ LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
+ num_instr++;
+ }
+
+ if (num_instr == 1) {
+ check_scalar(bc, alu_first);
+
+ } else {
+/* check_read_slots(bc, bc->cf_last->curr_bs_head);*/
+ check_vector(bc, alu_first);
+ LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
+ check_vector(bc, alu);
+ }
+ }
+ return 0;
+}
+
+int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)