- /* Check constant buffers. */
- unsigned shader;
- for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
- struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
- uint32_t mask = state->enabled_mask;
-
- while (mask) {
- unsigned i = u_bit_scan(&mask);
- if (state->cb[i].buffer == res) {
- rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
-
- shader = PIPE_SHADER_TYPES; /* break the outer loop */
- break;
- }
- }
- }
-
- /* Check textures. */
- for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
- struct r600_samplerview_state *state = &rctx->samplers[shader].views;
- uint32_t mask = state->enabled_mask;
-
- while (mask) {
- uint32_t i = u_bit_scan(&mask);
- if (&state->views[i]->tex_resource->b.b == res) {
- rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
-
- shader = PIPE_SHADER_TYPES; /* break the outer loop */
- break;
- }
- }
- }
-
- /* Check streamout buffers. */
- int i;
- for (i = 0; i < rctx->b.streamout.num_targets; i++) {
- if (rctx->b.streamout.targets[i]->b.buffer == res) {
- rctx->b.flags |= R600_CONTEXT_STREAMOUT_FLUSH |
- R600_CONTEXT_FLUSH_AND_INV |
- R600_CONTEXT_WAIT_3D_IDLE;
- break;
- }
- }
-
- /* Check colorbuffers. */
- for (i = 0; i < rctx->framebuffer.state.nr_cbufs; i++) {
- struct r600_texture *tex;
-
- if (rctx->framebuffer.state.cbufs[i] == NULL) {
- continue;
- }
-
- tex = (struct r600_texture*)rctx->framebuffer.state.cbufs[i]->texture;
-
- if (rctx->framebuffer.state.cbufs[i]->texture == res) {
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
- R600_CONTEXT_FLUSH_AND_INV |
- R600_CONTEXT_WAIT_3D_IDLE;
-
- if (tex->cmask_size || tex->fmask_size) {
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
- }
- break;
- }
-
- if (tex && tex->cmask && tex->cmask != &tex->resource && &tex->cmask->b.b == res) {
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META |
- R600_CONTEXT_FLUSH_AND_INV |
- R600_CONTEXT_WAIT_3D_IDLE;
- }
- }
-
- /* Check a depth buffer. */
- if (rctx->framebuffer.state.zsbuf) {
- if (rctx->framebuffer.state.zsbuf->texture == res) {
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
- R600_CONTEXT_FLUSH_AND_INV |
- R600_CONTEXT_WAIT_3D_IDLE;
- }
-
- struct r600_texture *tex =
- (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
- if (tex && tex->htile && &tex->htile->b.b == res) {
- rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META |
- R600_CONTEXT_FLUSH_AND_INV |
- R600_CONTEXT_WAIT_3D_IDLE;
- }
+ r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
+ for (i = 0; i < ncopy; i++) {
+ csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW;
+ /* emit reloc before writing cs so that cs is always in consistent state */
+ radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ,
+ RADEON_PRIO_SDMA_BUFFER);
+ radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_SDMA_BUFFER);
+ radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize));
+ radeon_emit(cs, dst_offset & 0xfffffffc);
+ radeon_emit(cs, src_offset & 0xfffffffc);
+ radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
+ radeon_emit(cs, (src_offset >> 32UL) & 0xff);
+ dst_offset += csize << 2;
+ src_offset += csize << 2;
+ size -= csize;