-boolean r600_is_format_supported(struct pipe_screen *screen,
- enum pipe_format format,
- enum pipe_texture_target target,
- unsigned sample_count,
- unsigned usage)
+bool r600_is_format_supported(struct pipe_screen *screen,
+ enum pipe_format format,
+ enum pipe_texture_target target,
+ unsigned sample_count,
+ unsigned storage_sample_count,
+ unsigned usage)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
unsigned retval = 0;
if (target >= PIPE_MAX_TEXTURE_TYPES) {
R600_ERR("r600: unsupported texture type %d\n", target);
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
unsigned retval = 0;
if (target >= PIPE_MAX_TEXTURE_TYPES) {
R600_ERR("r600: unsupported texture type %d\n", target);
/* R11G11B10 is broken on R6xx. */
if (rscreen->b.chip_class == R600 &&
format == PIPE_FORMAT_R11G11B10_FLOAT)
/* R11G11B10 is broken on R6xx. */
if (rscreen->b.chip_class == R600 &&
format == PIPE_FORMAT_R11G11B10_FLOAT)
/* MSAA integer colorbuffers hang. */
if (util_format_is_pure_integer(format) &&
!util_format_is_depth_or_stencil(format))
/* MSAA integer colorbuffers hang. */
if (util_format_is_pure_integer(format) &&
!util_format_is_depth_or_stencil(format))
S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
rs->pa_cl_clip_cntl =
S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
rs->pa_cl_clip_cntl =
S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
- S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
- S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
+ S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
+ S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
};
FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
};
FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
};
FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
};
FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
};
FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
};
radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc_idx);
} else {
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc_idx);
} else {
- if (rview) {
- enum pipe_texture_target target = rview->base.texture->target;
- if (target == PIPE_TEXTURE_1D_ARRAY ||
- target == PIPE_TEXTURE_2D_ARRAY) {
- rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
- texinfo->is_array_sampler[i] = true;
- } else {
- rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
- texinfo->is_array_sampler[i] = false;
- }
+ enum pipe_texture_target target = PIPE_BUFFER;
+ if (rview)
+ target = rview->base.texture->target;
+ if (target == PIPE_TEXTURE_1D_ARRAY ||
+ target == PIPE_TEXTURE_2D_ARRAY) {
+ rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
+ texinfo->is_array_sampler[i] = true;
+ } else {
+ rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
+ texinfo->is_array_sampler[i] = false;
}
radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
}
radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
cheight = cheight > copy_height ? copy_height : cheight;
size = (cheight * pitch) / 4;
/* emit reloc before writing cs so that cs is always in consistent state */
cheight = cheight > copy_height ? copy_height : cheight;
size = (cheight * pitch) / 4;
/* emit reloc before writing cs so that cs is always in consistent state */
- radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
- RADEON_PRIO_SDMA_TEXTURE);
- radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
- RADEON_PRIO_SDMA_TEXTURE);
+ radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ, 0);
+ radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE, 0);
radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
radeon_emit(cs, base >> 8);
radeon_emit(cs, (detile << 31) | (array_mode << 27) |
radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
radeon_emit(cs, base >> 8);
radeon_emit(cs, (detile << 31) | (array_mode << 27) |