+ p_atomic_inc(&sctx->screen->dirty_tex_counter);
+}
+
+static uint32_t si_get_bo_metadata_word1(struct si_screen *sscreen)
+{
+ return (ATI_VENDOR_ID << 16) | sscreen->info.pci_id;
+}
+
+static void si_query_opaque_metadata(struct si_screen *sscreen,
+ struct r600_texture *rtex,
+ struct radeon_bo_metadata *md)
+{
+ struct pipe_resource *res = &rtex->resource.b.b;
+ static const unsigned char swizzle[] = {
+ PIPE_SWIZZLE_X,
+ PIPE_SWIZZLE_Y,
+ PIPE_SWIZZLE_Z,
+ PIPE_SWIZZLE_W
+ };
+ uint32_t desc[8], i;
+ bool is_array = util_texture_is_array(res->target);
+
+ /* DRM 2.x.x doesn't support this. */
+ if (sscreen->info.drm_major != 3)
+ return;
+
+ assert(rtex->dcc_separate_buffer == NULL);
+ assert(rtex->fmask.size == 0);
+
+ /* Metadata image format format version 1:
+ * [0] = 1 (metadata format identifier)
+ * [1] = (VENDOR_ID << 16) | PCI_ID
+ * [2:9] = image descriptor for the whole resource
+ * [2] is always 0, because the base address is cleared
+ * [9] is the DCC offset bits [39:8] from the beginning of
+ * the buffer
+ * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
+ */
+
+ md->metadata[0] = 1; /* metadata image format version 1 */
+
+ /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
+ md->metadata[1] = si_get_bo_metadata_word1(sscreen);
+
+ si_make_texture_descriptor(sscreen, rtex, true,
+ res->target, res->format,
+ swizzle, 0, res->last_level, 0,
+ is_array ? res->array_size - 1 : 0,
+ res->width0, res->height0, res->depth0,
+ desc, NULL);
+
+ si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
+ 0, 0, rtex->surface.blk_w, false, desc);
+
+ /* Clear the base address and set the relative DCC offset. */
+ desc[0] = 0;
+ desc[1] &= C_008F14_BASE_ADDRESS_HI;
+ desc[7] = rtex->dcc_offset >> 8;
+
+ /* Dwords [2:9] contain the image descriptor. */
+ memcpy(&md->metadata[2], desc, sizeof(desc));
+ md->size_metadata = 10 * 4;
+
+ /* Dwords [10:..] contain the mipmap level offsets. */
+ if (sscreen->info.chip_class <= VI) {
+ for (i = 0; i <= res->last_level; i++)
+ md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
+
+ md->size_metadata += (1 + res->last_level) * 4;
+ }
+}
+
+static void si_apply_opaque_metadata(struct si_screen *sscreen,
+ struct r600_texture *rtex,
+ struct radeon_bo_metadata *md)
+{
+ uint32_t *desc = &md->metadata[2];
+
+ if (sscreen->info.chip_class < VI)
+ return;
+
+ /* Return if DCC is enabled. The texture should be set up with it
+ * already.
+ */
+ if (md->size_metadata >= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
+ md->metadata[0] != 0 &&
+ md->metadata[1] == si_get_bo_metadata_word1(sscreen) &&
+ G_008F28_COMPRESSION_EN(desc[6])) {
+ rtex->dcc_offset = (uint64_t)desc[7] << 8;
+ return;
+ }
+
+ /* Disable DCC. These are always set by texture_from_handle and must
+ * be cleared here.
+ */
+ rtex->dcc_offset = 0;