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winsys/radeon: use the common job queue for multithreaded command submission v2
[mesa.git]
/
src
/
gallium
/
drivers
/
radeon
/
radeon_video.c
diff --git
a/src/gallium/drivers/radeon/radeon_video.c
b/src/gallium/drivers/radeon/radeon_video.c
index ec29d8cb75415999e9a222650d6527d5d4495b93..aba1404d1cb16caaeaebf322e9459fdb665d8915 100644
(file)
--- a/
src/gallium/drivers/radeon/radeon_video.c
+++ b/
src/gallium/drivers/radeon/radeon_video.c
@@
-122,7
+122,7
@@
void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
struct r600_common_context *rctx = (struct r600_common_context*)context;
rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size,
struct r600_common_context *rctx = (struct r600_common_context*)context;
rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size,
- 0,
false
);
+ 0,
R600_COHERENCY_NONE
);
context->flush(context, NULL, 0);
}
context->flush(context, NULL, 0);
}
@@
-130,7
+130,7
@@
void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
* join surfaces into the same buffer with identical tiling params
* sumup their sizes and replace the backend buffers with a single bo
*/
* join surfaces into the same buffer with identical tiling params
* sumup their sizes and replace the backend buffers with a single bo
*/
-void rvid_join_surfaces(struct radeon_winsys* ws,
unsigned bind,
+void rvid_join_surfaces(struct radeon_winsys* ws,
struct pb_buffer** buffers[VL_NUM_COMPONENTS],
struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
{
struct pb_buffer** buffers[VL_NUM_COMPONENTS],
struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
{
@@
-165,7
+165,7
@@
void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
/* adjust the texture layer offsets */
off = align(off, surfaces[i]->bo_alignment);
/* adjust the texture layer offsets */
off = align(off, surfaces[i]->bo_alignment);
- for (j = 0; j <
Elements
(surfaces[i]->level); ++j)
+ for (j = 0; j <
ARRAY_SIZE
(surfaces[i]->level); ++j)
surfaces[i]->level[j].offset += off;
off += surfaces[i]->bo_size;
}
surfaces[i]->level[j].offset += off;
off += surfaces[i]->bo_size;
}
@@
-185,7
+185,7
@@
void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
/* TODO: 2D tiling workaround */
alignment *= 2;
/* TODO: 2D tiling workaround */
alignment *= 2;
- pb = ws->buffer_create(ws, size, alignment,
bind,
RADEON_DOMAIN_VRAM, 0);
+ pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
if (!pb)
return;
if (!pb)
return;
@@
-237,6
+237,7
@@
int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_CAP_SUPPORTED:
switch (codec) {
case PIPE_VIDEO_FORMAT_MPEG12:
case PIPE_VIDEO_CAP_SUPPORTED:
switch (codec) {
case PIPE_VIDEO_FORMAT_MPEG12:
+ return profile != PIPE_VIDEO_PROFILE_MPEG1;
case PIPE_VIDEO_FORMAT_MPEG4:
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
if (rscreen->family < CHIP_PALM)
case PIPE_VIDEO_FORMAT_MPEG4:
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
if (rscreen->family < CHIP_PALM)
@@
-247,8
+248,11
@@
int rvid_get_video_param(struct pipe_screen *screen,
return true;
case PIPE_VIDEO_FORMAT_HEVC:
/* Carrizo only supports HEVC Main */
return true;
case PIPE_VIDEO_FORMAT_HEVC:
/* Carrizo only supports HEVC Main */
- return rscreen->family >= CHIP_CARRIZO &&
- profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
+ if (rscreen->family >= CHIP_STONEY)
+ return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
+ profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
+ else if (rscreen->family >= CHIP_CARRIZO)
+ return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
default:
return false;
}
default:
return false;
}
@@
-257,7
+261,7
@@
int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_CAP_MAX_WIDTH:
return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
case PIPE_VIDEO_CAP_MAX_HEIGHT:
case PIPE_VIDEO_CAP_MAX_WIDTH:
return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
case PIPE_VIDEO_CAP_MAX_HEIGHT:
- return (rscreen->family < CHIP_TONGA) ? 1152 :
2304
;
+ return (rscreen->family < CHIP_TONGA) ? 1152 :
4096
;
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
@@
-294,8
+298,9
@@
int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
- return
41
;
+ return
(rscreen->family < CHIP_TONGA) ? 41 : 52
;
case PIPE_VIDEO_PROFILE_HEVC_MAIN:
case PIPE_VIDEO_PROFILE_HEVC_MAIN:
+ case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
return 186;
default:
return 0;
return 186;
default:
return 0;