+enum radeon_heap {
+ RADEON_HEAP_VRAM_NO_CPU_ACCESS,
+ RADEON_HEAP_VRAM_READ_ONLY,
+ RADEON_HEAP_VRAM_READ_ONLY_32BIT,
+ RADEON_HEAP_VRAM_32BIT,
+ RADEON_HEAP_VRAM,
+ RADEON_HEAP_GTT_WC,
+ RADEON_HEAP_GTT_WC_READ_ONLY,
+ RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
+ RADEON_HEAP_GTT_WC_32BIT,
+ RADEON_HEAP_GTT,
+ RADEON_MAX_SLAB_HEAPS,
+ RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
+};
+
+static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
+{
+ switch (heap) {
+ case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+ case RADEON_HEAP_VRAM_READ_ONLY:
+ case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
+ case RADEON_HEAP_VRAM_32BIT:
+ case RADEON_HEAP_VRAM:
+ return RADEON_DOMAIN_VRAM;
+ case RADEON_HEAP_GTT_WC:
+ case RADEON_HEAP_GTT_WC_READ_ONLY:
+ case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
+ case RADEON_HEAP_GTT_WC_32BIT:
+ case RADEON_HEAP_GTT:
+ return RADEON_DOMAIN_GTT;
+ default:
+ assert(0);
+ return (enum radeon_bo_domain)0;
+ }
+}
+
+static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
+{
+ unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
+
+ switch (heap) {
+ case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+ return flags |
+ RADEON_FLAG_NO_CPU_ACCESS;
+
+ case RADEON_HEAP_VRAM_READ_ONLY:
+ case RADEON_HEAP_GTT_WC_READ_ONLY:
+ return flags |
+ RADEON_FLAG_READ_ONLY;
+
+ case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
+ case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
+ return flags |
+ RADEON_FLAG_READ_ONLY |
+ RADEON_FLAG_32BIT;
+
+ case RADEON_HEAP_VRAM_32BIT:
+ case RADEON_HEAP_GTT_WC_32BIT:
+ return flags |
+ RADEON_FLAG_32BIT;
+
+ case RADEON_HEAP_VRAM:
+ case RADEON_HEAP_GTT_WC:
+ case RADEON_HEAP_GTT:
+ default:
+ return flags;
+ }
+}
+
+/* Return the heap index for winsys allocators, or -1 on failure. */
+static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
+ enum radeon_bo_flag flags)
+{
+ /* VRAM implies WC (write combining) */
+ assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
+ /* NO_CPU_ACCESS implies VRAM only. */
+ assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
+
+ /* Resources with interprocess sharing don't use any winsys allocators. */
+ if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
+ return -1;
+
+ /* Unsupported flags: NO_SUBALLOC, SPARSE. */
+ if (flags & ~(RADEON_FLAG_GTT_WC |
+ RADEON_FLAG_NO_CPU_ACCESS |
+ RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ RADEON_FLAG_READ_ONLY |
+ RADEON_FLAG_32BIT))
+ return -1;
+
+ switch (domain) {
+ case RADEON_DOMAIN_VRAM:
+ switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
+ RADEON_FLAG_READ_ONLY |
+ RADEON_FLAG_32BIT)) {
+ case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+ case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
+ assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
+ return -1;
+ case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
+ assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
+ return -1;
+ case RADEON_FLAG_NO_CPU_ACCESS:
+ return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
+ case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+ return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
+ case RADEON_FLAG_READ_ONLY:
+ return RADEON_HEAP_VRAM_READ_ONLY;
+ case RADEON_FLAG_32BIT:
+ return RADEON_HEAP_VRAM_32BIT;
+ case 0:
+ return RADEON_HEAP_VRAM;
+ }
+ break;
+ case RADEON_DOMAIN_GTT:
+ switch (flags & (RADEON_FLAG_GTT_WC |
+ RADEON_FLAG_READ_ONLY |
+ RADEON_FLAG_32BIT)) {
+ case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+ return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
+ case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
+ return RADEON_HEAP_GTT_WC_READ_ONLY;
+ case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
+ return RADEON_HEAP_GTT_WC_32BIT;
+ case RADEON_FLAG_GTT_WC:
+ return RADEON_HEAP_GTT_WC;
+ case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+ case RADEON_FLAG_READ_ONLY:
+ assert(!"READ_ONLY without WC is disallowed");
+ return -1;
+ case RADEON_FLAG_32BIT:
+ assert(!"32BIT without WC is disallowed");
+ return -1;
+ case 0:
+ return RADEON_HEAP_GTT;
+ }
+ break;
+ default:
+ break;
+ }
+ return -1;
+}
+