- struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
- struct si_screen *sscreen = ctx->screen;
- struct r600_texture *rsrc = (struct r600_texture*)src;
- struct r600_texture *rdst = (struct r600_texture*)dst;
- struct r600_texture *rlinear, *rtiled;
- unsigned linear_lvl, tiled_lvl;
- unsigned array_mode, lbpe, pitch_tile_max, slice_tile_max, size;
- unsigned ncopy, height, cheight, detile, i, src_mode, dst_mode;
- unsigned sub_op, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
- uint64_t base, addr;
- unsigned pipe_config, tile_mode_index;
-
- dst_mode = rdst->surface.level[dst_level].mode;
- src_mode = rsrc->surface.level[src_level].mode;
- /* downcast linear aligned to linear to simplify test */
- src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
- dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
- assert(dst_mode != src_mode);
- assert(src_mode == RADEON_SURF_MODE_LINEAR || dst_mode == RADEON_SURF_MODE_LINEAR);
-
- sub_op = CIK_SDMA_COPY_SUB_OPCODE_TILED;
- lbpe = util_logbase2(bpe);
- pitch_tile_max = ((pitch / bpe) / 8) - 1;
-
- detile = dst_mode == RADEON_SURF_MODE_LINEAR;
- rlinear = detile ? rdst : rsrc;
- rtiled = detile ? rsrc : rdst;
- linear_lvl = detile ? dst_level : src_level;
- tiled_lvl = detile ? src_level : dst_level;
-
- assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format));
-
- array_mode = si_array_mode(rtiled->surface.level[tiled_lvl].mode);
- slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x *
- rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1;
- height = rlinear->surface.level[linear_lvl].nblk_y;
- base = rtiled->surface.level[tiled_lvl].offset;
- addr = rlinear->surface.level[linear_lvl].offset;
- bank_h = cik_bank_wh(rtiled->surface.bankh);
- bank_w = cik_bank_wh(rtiled->surface.bankw);
- mt_aspect = cik_macro_tile_aspect(rtiled->surface.mtilea);
- tile_split = cik_tile_split(rtiled->surface.tile_split);
- tile_mode_index = si_tile_mode_index(rtiled, tiled_lvl, false);
- nbanks = si_num_banks(sscreen, rtiled);
- base += rtiled->resource.gpu_address;
- addr += rlinear->resource.gpu_address;
-
- pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
- mt = cik_micro_tile_mode(sscreen, tile_mode_index);
-
- size = (copy_height * pitch) / 4;
- cheight = copy_height;
- if (((cheight * pitch) / 4) > CIK_SDMA_COPY_MAX_SIZE) {
- cheight = (CIK_SDMA_COPY_MAX_SIZE * 4) / pitch;
- cheight &= ~(y_align - 1);
- }
- ncopy = (copy_height + cheight - 1) / cheight;
- r600_need_dma_space(&ctx->b, ncopy * 12);
-
- r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
- RADEON_USAGE_READ, RADEON_PRIO_MIN);
- r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
- RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
-
- copy_height = size * 4 / pitch;
- for (i = 0; i < ncopy; i++) {
- cheight = copy_height;
- if (((cheight * pitch) / 4) > CIK_SDMA_COPY_MAX_SIZE) {
- cheight = (CIK_SDMA_COPY_MAX_SIZE * 4) / pitch;
- cheight &= ~(y_align - 1);
- }
- size = (cheight * pitch) / 4;
-
- cs->buf[cs->cdw++] = CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
- sub_op, detile << 15);
- cs->buf[cs->cdw++] = base;
- cs->buf[cs->cdw++] = base >> 32;
- cs->buf[cs->cdw++] = ((height - 1) << 16) | pitch_tile_max;
- cs->buf[cs->cdw++] = slice_tile_max;
- cs->buf[cs->cdw++] = (pipe_config << 26) | (mt_aspect << 24) |
- (nbanks << 21) | (bank_h << 18) | (bank_w << 15) |
- (tile_split << 11) | (mt << 8) | (array_mode << 3) |
- lbpe;
- cs->buf[cs->cdw++] = y << 16; /* | x */
- cs->buf[cs->cdw++] = 0; /* z */;
- cs->buf[cs->cdw++] = addr & 0xfffffffc;
- cs->buf[cs->cdw++] = addr >> 32;
- cs->buf[cs->cdw++] = (pitch / bpe) - 1;
- cs->buf[cs->cdw++] = size;
-
- copy_height -= cheight;
- y += cheight;
- }
+ struct radeon_info *info = &sctx->screen->info;
+ struct si_texture *ssrc = (struct si_texture *)src;
+ struct si_texture *sdst = (struct si_texture *)dst;
+ unsigned bpp = sdst->surface.bpe;
+ uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.legacy.level[dst_level].offset;
+ uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.legacy.level[src_level].offset;
+ unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
+ unsigned src_mode = ssrc->surface.u.legacy.level[src_level].mode;
+ unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[dst_level];
+ unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[src_level];
+ unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
+ unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
+ unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
+ unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
+ unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ? sdst->surface.tile_swizzle : 0;
+ unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ? ssrc->surface.tile_swizzle : 0;
+ unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x;
+ unsigned src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x;
+ uint64_t dst_slice_pitch =
+ ((uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
+ uint64_t src_slice_pitch =
+ ((uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
+ unsigned dst_width = minify_as_blocks(sdst->buffer.b.b.width0, dst_level, sdst->surface.blk_w);
+ unsigned src_width = minify_as_blocks(ssrc->buffer.b.b.width0, src_level, ssrc->surface.blk_w);
+ unsigned dst_height = minify_as_blocks(sdst->buffer.b.b.height0, dst_level, sdst->surface.blk_h);
+ unsigned src_height = minify_as_blocks(ssrc->buffer.b.b.height0, src_level, ssrc->surface.blk_h);
+ unsigned srcx = src_box->x / ssrc->surface.blk_w;
+ unsigned srcy = src_box->y / ssrc->surface.blk_h;
+ unsigned srcz = src_box->z;
+ unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
+ unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
+ unsigned copy_depth = src_box->depth;
+
+ assert(src_level <= src->last_level);
+ assert(dst_level <= dst->last_level);
+ assert(sdst->surface.u.legacy.level[dst_level].offset +
+ dst_slice_pitch * bpp * (dstz + src_box->depth) <=
+ sdst->buffer.buf->size);
+ assert(ssrc->surface.u.legacy.level[src_level].offset +
+ src_slice_pitch * bpp * (srcz + src_box->depth) <=
+ ssrc->buffer.buf->size);
+
+ if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty, dstz, ssrc, src_level, src_box))
+ return false;
+
+ dstx /= sdst->surface.blk_w;
+ dsty /= sdst->surface.blk_h;
+
+ if (srcx >= (1 << 14) || srcy >= (1 << 14) || srcz >= (1 << 11) || dstx >= (1 << 14) ||
+ dsty >= (1 << 14) || dstz >= (1 << 11))
+ return false;
+
+ dst_address |= dst_tile_swizzle << 8;
+ src_address |= src_tile_swizzle << 8;
+
+ /* Linear -> linear sub-window copy. */
+ if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED && src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
+ /* check if everything fits into the bitfields */
+ src_pitch <= (1 << 14) && dst_pitch <= (1 << 14) && src_slice_pitch <= (1 << 28) &&
+ dst_slice_pitch <= (1 << 28) && copy_width <= (1 << 14) && copy_height <= (1 << 14) &&
+ copy_depth <= (1 << 11) &&
+ /* HW limitation - GFX7: */
+ (sctx->chip_class != GFX7 ||
+ (copy_width < (1 << 14) && copy_height < (1 << 14) && copy_depth < (1 << 11))) &&
+ /* HW limitation - some GFX7 parts: */
+ ((sctx->family != CHIP_BONAIRE && sctx->family != CHIP_KAVERI) ||
+ (srcx + copy_width != (1 << 14) && srcy + copy_height != (1 << 14)))) {
+ struct radeon_cmdbuf *cs = sctx->sdma_cs;
+
+ si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
+
+ radeon_emit(
+ cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
+ (util_logbase2(bpp) << 29));
+ radeon_emit(cs, src_address);
+ radeon_emit(cs, src_address >> 32);
+ radeon_emit(cs, srcx | (srcy << 16));
+ radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
+ radeon_emit(cs, src_slice_pitch - 1);
+ radeon_emit(cs, dst_address);
+ radeon_emit(cs, dst_address >> 32);
+ radeon_emit(cs, dstx | (dsty << 16));
+ radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
+ radeon_emit(cs, dst_slice_pitch - 1);
+ if (sctx->chip_class == GFX7) {
+ radeon_emit(cs, copy_width | (copy_height << 16));
+ radeon_emit(cs, copy_depth);
+ } else {
+ radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
+ radeon_emit(cs, (copy_depth - 1));
+ }
+ return true;
+ }
+
+ /* Tiled <-> linear sub-window copy. */
+ if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
+ struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst;
+ struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
+ unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
+ unsigned linear_level = linear == ssrc ? src_level : dst_level;
+ unsigned tiled_x = tiled == ssrc ? srcx : dstx;
+ unsigned linear_x = linear == ssrc ? srcx : dstx;
+ unsigned tiled_y = tiled == ssrc ? srcy : dsty;
+ unsigned linear_y = linear == ssrc ? srcy : dsty;
+ unsigned tiled_z = tiled == ssrc ? srcz : dstz;
+ unsigned linear_z = linear == ssrc ? srcz : dstz;
+ unsigned tiled_width = tiled == ssrc ? src_width : dst_width;
+ unsigned linear_width = linear == ssrc ? src_width : dst_width;
+ unsigned tiled_pitch = tiled == ssrc ? src_pitch : dst_pitch;
+ unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
+ unsigned tiled_slice_pitch = tiled == ssrc ? src_slice_pitch : dst_slice_pitch;
+ unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
+ uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
+ uint64_t linear_address = linear == ssrc ? src_address : dst_address;
+ unsigned tiled_micro_mode = tiled == ssrc ? src_micro_mode : dst_micro_mode;
+
+ assert(tiled_pitch % 8 == 0);
+ assert(tiled_slice_pitch % 64 == 0);
+ unsigned pitch_tile_max = tiled_pitch / 8 - 1;
+ unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
+ unsigned xalign = MAX2(1, 4 / bpp);
+ unsigned copy_width_aligned = copy_width;
+
+ /* If the region ends at the last pixel and is unaligned, we
+ * can copy the remainder of the line that is not visible to
+ * make it aligned.
+ */
+ if (copy_width % xalign != 0 && linear_x + copy_width == linear_width &&
+ tiled_x + copy_width == tiled_width &&
+ linear_x + align(copy_width, xalign) <= linear_pitch &&
+ tiled_x + align(copy_width, xalign) <= tiled_pitch)
+ copy_width_aligned = align(copy_width, xalign);
+
+ /* HW limitations. */
+ if ((sctx->family == CHIP_BONAIRE || sctx->family == CHIP_KAVERI) &&
+ linear_pitch - 1 == 0x3fff && bpp == 16)
+ return false;
+
+ if (sctx->chip_class == GFX7 &&
+ (copy_width_aligned == (1 << 14) || copy_height == (1 << 14) || copy_depth == (1 << 11)))
+ return false;
+
+ if ((sctx->family == CHIP_BONAIRE || sctx->family == CHIP_KAVERI ||
+ sctx->family == CHIP_KABINI) &&
+ (tiled_x + copy_width == (1 << 14) || tiled_y + copy_height == (1 << 14)))
+ return false;
+
+ /* The hw can read outside of the given linear buffer bounds,
+ * or access those pages but not touch the memory in case
+ * of writes. (it still causes a VM fault)
+ *
+ * Out-of-bounds memory access or page directory access must
+ * be prevented.
+ */
+ int64_t start_linear_address, end_linear_address;
+ unsigned granularity;
+
+ /* Deduce the size of reads from the linear surface. */
+ switch (tiled_micro_mode) {
+ case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
+ granularity = bpp == 1 ? 64 / (8 * bpp) : 128 / (8 * bpp);
+ break;
+ case V_009910_ADDR_SURF_THIN_MICRO_TILING:
+ case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
+ if (0 /* TODO: THICK microtiling */)
+ granularity =
+ bpp == 1 ? 32 / (8 * bpp)
+ : bpp == 2 ? 64 / (8 * bpp) : bpp <= 8 ? 128 / (8 * bpp) : 256 / (8 * bpp);
+ else
+ granularity = bpp <= 2 ? 64 / (8 * bpp) : bpp <= 8 ? 128 / (8 * bpp) : 256 / (8 * bpp);
+ break;
+ default:
+ return false;
+ }
+
+ /* The linear reads start at tiled_x & ~(granularity - 1).
+ * If linear_x == 0 && tiled_x % granularity != 0, the hw
+ * starts reading from an address preceding linear_address!!!
+ */
+ start_linear_address =
+ linear->surface.u.legacy.level[linear_level].offset +
+ bpp * (linear_z * linear_slice_pitch + linear_y * linear_pitch + linear_x);
+ start_linear_address -= (int)(bpp * (tiled_x % granularity));
+
+ end_linear_address =
+ linear->surface.u.legacy.level[linear_level].offset +
+ bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
+ (linear_y + copy_height - 1) * linear_pitch + (linear_x + copy_width));
+
+ if ((tiled_x + copy_width) % granularity)
+ end_linear_address += granularity - (tiled_x + copy_width) % granularity;
+
+ if (start_linear_address < 0 || end_linear_address > linear->surface.surf_size)
+ return false;
+
+ /* Check requirements. */
+ if (tiled_address % 256 == 0 && linear_address % 4 == 0 && linear_pitch % xalign == 0 &&
+ linear_x % xalign == 0 && tiled_x % xalign == 0 && copy_width_aligned % xalign == 0 &&
+ tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
+ /* check if everything fits into the bitfields */
+ tiled->surface.u.legacy.tile_split <= 4096 && pitch_tile_max < (1 << 11) &&
+ slice_tile_max < (1 << 22) && linear_pitch <= (1 << 14) &&
+ linear_slice_pitch <= (1 << 28) && copy_width_aligned <= (1 << 14) &&
+ copy_height <= (1 << 14) && copy_depth <= (1 << 11)) {
+ struct radeon_cmdbuf *cs = sctx->sdma_cs;
+ uint32_t direction = linear == sdst ? 1u << 31 : 0;
+
+ si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
+
+ radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
+ CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
+ direction);
+ radeon_emit(cs, tiled_address);
+ radeon_emit(cs, tiled_address >> 32);
+ radeon_emit(cs, tiled_x | (tiled_y << 16));
+ radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
+ radeon_emit(cs, slice_tile_max);
+ radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
+ radeon_emit(cs, linear_address);
+ radeon_emit(cs, linear_address >> 32);
+ radeon_emit(cs, linear_x | (linear_y << 16));
+ radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
+ radeon_emit(cs, linear_slice_pitch - 1);
+ if (sctx->chip_class == GFX7) {
+ radeon_emit(cs, copy_width_aligned | (copy_height << 16));
+ radeon_emit(cs, copy_depth);
+ } else {
+ radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
+ radeon_emit(cs, (copy_depth - 1));
+ }
+ return true;
+ }
+ }
+
+ /* Tiled -> Tiled sub-window copy. */
+ if (dst_mode >= RADEON_SURF_MODE_1D && src_mode >= RADEON_SURF_MODE_1D &&
+ /* check if these fit into the bitfields */
+ src_address % 256 == 0 && dst_address % 256 == 0 &&
+ ssrc->surface.u.legacy.tile_split <= 4096 && sdst->surface.u.legacy.tile_split <= 4096 &&
+ dstx % 8 == 0 && dsty % 8 == 0 && srcx % 8 == 0 && srcy % 8 == 0 &&
+ /* this can either be equal, or display->rotated (GFX8+ only) */
+ (src_micro_mode == dst_micro_mode ||
+ (sctx->chip_class >= GFX8 && src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
+ dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
+ assert(src_pitch % 8 == 0);
+ assert(dst_pitch % 8 == 0);
+ assert(src_slice_pitch % 64 == 0);
+ assert(dst_slice_pitch % 64 == 0);
+ unsigned src_pitch_tile_max = src_pitch / 8 - 1;
+ unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
+ unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
+ unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
+ unsigned copy_width_aligned = copy_width;
+ unsigned copy_height_aligned = copy_height;
+
+ /* If the region ends at the last pixel and is unaligned, we
+ * can copy the remainder of the tile that is not visible to
+ * make it aligned.
+ */
+ if (copy_width % 8 != 0 && srcx + copy_width == src_width && dstx + copy_width == dst_width)
+ copy_width_aligned = align(copy_width, 8);
+
+ if (copy_height % 8 != 0 && srcy + copy_height == src_height &&
+ dsty + copy_height == dst_height)
+ copy_height_aligned = align(copy_height, 8);
+
+ /* check if these fit into the bitfields */
+ if (src_pitch_tile_max < (1 << 11) && dst_pitch_tile_max < (1 << 11) &&
+ src_slice_tile_max < (1 << 22) && dst_slice_tile_max < (1 << 22) &&
+ copy_width_aligned <= (1 << 14) && copy_height_aligned <= (1 << 14) &&
+ copy_depth <= (1 << 11) && copy_width_aligned % 8 == 0 && copy_height_aligned % 8 == 0 &&
+ /* HW limitation - GFX7: */
+ (sctx->chip_class != GFX7 ||
+ (copy_width_aligned < (1 << 14) && copy_height_aligned < (1 << 14) &&
+ copy_depth < (1 << 11))) &&
+ /* HW limitation - some GFX7 parts: */
+ ((sctx->family != CHIP_BONAIRE && sctx->family != CHIP_KAVERI &&
+ sctx->family != CHIP_KABINI) ||
+ (srcx + copy_width_aligned != (1 << 14) && srcy + copy_height_aligned != (1 << 14) &&
+ dstx + copy_width != (1 << 14)))) {
+ struct radeon_cmdbuf *cs = sctx->sdma_cs;
+
+ si_need_dma_space(sctx, 15, &sdst->buffer, &ssrc->buffer);
+
+ radeon_emit(
+ cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
+ radeon_emit(cs, src_address);
+ radeon_emit(cs, src_address >> 32);
+ radeon_emit(cs, srcx | (srcy << 16));
+ radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
+ radeon_emit(cs, src_slice_tile_max);
+ radeon_emit(cs, encode_tile_info(sctx, ssrc, src_level, true));
+ radeon_emit(cs, dst_address);
+ radeon_emit(cs, dst_address >> 32);
+ radeon_emit(cs, dstx | (dsty << 16));
+ radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
+ radeon_emit(cs, dst_slice_tile_max);
+ radeon_emit(cs, encode_tile_info(sctx, sdst, dst_level, false));
+ if (sctx->chip_class == GFX7) {
+ radeon_emit(cs, copy_width_aligned | (copy_height_aligned << 16));
+ radeon_emit(cs, copy_depth);
+ } else {
+ radeon_emit(cs, (copy_width_aligned - 8) | ((copy_height_aligned - 8) << 16));
+ radeon_emit(cs, (copy_depth - 1));
+ }
+ return true;
+ }
+ }
+
+ return false;