- struct radeon_cmdbuf *cs = sctx->gfx_cs;
-
- if (((sctx->tracked_regs.reg_saved >> reg) & 0xf) != 0xf ||
- sctx->tracked_regs.reg_value[reg] != value1 ||
- sctx->tracked_regs.reg_value[reg+1] != value2 ||
- sctx->tracked_regs.reg_value[reg+2] != value3 ||
- sctx->tracked_regs.reg_value[reg+3] != value4) {
- radeon_set_context_reg_seq(cs, offset, 4);
- radeon_emit(cs, value1);
- radeon_emit(cs, value2);
- radeon_emit(cs, value3);
- radeon_emit(cs, value4);
-
- sctx->tracked_regs.reg_value[reg] = value1;
- sctx->tracked_regs.reg_value[reg+1] = value2;
- sctx->tracked_regs.reg_value[reg+2] = value3;
- sctx->tracked_regs.reg_value[reg+3] = value4;
- sctx->tracked_regs.reg_saved |= 0xfull << reg;
- }
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
+
+ if (((sctx->tracked_regs.reg_saved >> reg) & 0xf) != 0xf ||
+ sctx->tracked_regs.reg_value[reg] != value1 ||
+ sctx->tracked_regs.reg_value[reg + 1] != value2 ||
+ sctx->tracked_regs.reg_value[reg + 2] != value3 ||
+ sctx->tracked_regs.reg_value[reg + 3] != value4) {
+ radeon_set_context_reg_seq(cs, offset, 4);
+ radeon_emit(cs, value1);
+ radeon_emit(cs, value2);
+ radeon_emit(cs, value3);
+ radeon_emit(cs, value4);
+
+ sctx->tracked_regs.reg_value[reg] = value1;
+ sctx->tracked_regs.reg_value[reg + 1] = value2;
+ sctx->tracked_regs.reg_value[reg + 2] = value3;
+ sctx->tracked_regs.reg_value[reg + 3] = value4;
+ sctx->tracked_regs.reg_saved |= 0xfull << reg;
+ }