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radeonsi: release tokens after creating the shader program
[mesa.git]
/
src
/
gallium
/
drivers
/
radeonsi
/
si_cp_dma.c
diff --git
a/src/gallium/drivers/radeonsi/si_cp_dma.c
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 3001353df27663d4edda4c91f73a8da63676ce7a..5993369d2da4a91455881e99c4fd7ca351c88afc 100644
(file)
--- a/
src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/
src/gallium/drivers/radeonsi/si_cp_dma.c
@@
-212,8
+212,8
@@
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
uint64_t size, unsigned value, unsigned user_flags,
enum si_coherency coher, enum si_cache_policy cache_policy)
{
uint64_t size, unsigned value, unsigned user_flags,
enum si_coherency coher, enum si_cache_policy cache_policy)
{
- struct si_resource *
r
dst = si_resource(dst);
- uint64_t va = (
rdst ? r
dst->gpu_address : 0) + offset;
+ struct si_resource *
s
dst = si_resource(dst);
+ uint64_t va = (
sdst ? s
dst->gpu_address : 0) + offset;
bool is_first = true;
assert(size && size % 4 == 0);
bool is_first = true;
assert(size && size % 4 == 0);
@@
-221,11
+221,11
@@
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
* that range. */
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
* that range. */
- if (
r
dst)
- util_range_add(&
r
dst->valid_buffer_range, offset, offset + size);
+ if (
s
dst)
+ util_range_add(&
s
dst->valid_buffer_range, offset, offset + size);
/* Flush the caches. */
/* Flush the caches. */
- if (
r
dst && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
+ if (
s
dst && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH |
si_get_flush_flags(sctx, coher, cache_policy);
sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH |
si_get_flush_flags(sctx, coher, cache_policy);
@@
-233,7
+233,7
@@
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
while (size) {
unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
while (size) {
unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
- unsigned dma_flags = CP_DMA_CLEAR | (
r
dst ? 0 : CP_DMA_DST_IS_GDS);
+ unsigned dma_flags = CP_DMA_CLEAR | (
s
dst ? 0 : CP_DMA_DST_IS_GDS);
si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, user_flags,
coher, &is_first, &dma_flags);
si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, user_flags,
coher, &is_first, &dma_flags);
@@
-245,8
+245,8
@@
void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
va += byte_count;
}
va += byte_count;
}
- if (
r
dst && cache_policy != L2_BYPASS)
-
r
dst->TC_L2_dirty = true;
+ if (
s
dst && cache_policy != L2_BYPASS)
+
s
dst->TC_L2_dirty = true;
/* If it's not a framebuffer fast clear... */
if (coher == SI_COHERENCY_SHADER)
/* If it's not a framebuffer fast clear... */
if (coher == SI_COHERENCY_SHADER)