-/** Reset descriptors of buffer resources after \p buf has been invalidated. */
-static void si_reset_buffer_resources(struct si_context *sctx,
- struct si_buffer_resources *buffers,
- unsigned descriptors_idx,
- unsigned slot_mask,
- struct pipe_resource *buf,
- uint64_t old_va,
- enum radeon_bo_usage usage,
- enum radeon_bo_priority priority)
-{
- struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
- unsigned mask = buffers->enabled_mask & slot_mask;
-
- while (mask) {
- unsigned i = u_bit_scan(&mask);
- if (buffers->buffers[i] == buf) {
- si_desc_reset_buffer_offset(&sctx->b.b,
- descs->list + i*4,
- old_va, buf);
- sctx->descriptors_dirty |= 1u << descriptors_idx;
-
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- (struct r600_resource *)buf,
- usage, priority, true);
- }
- }
-}
-
-static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
- uint64_t old_va)
-{
- struct si_context *sctx = (struct si_context*)ctx;
- struct r600_resource *rbuffer = r600_resource(buf);
- unsigned i, shader;
- unsigned num_elems = sctx->vertex_elements ?
- sctx->vertex_elements->count : 0;
-
- /* We changed the buffer, now we need to bind it where the old one
- * was bound. This consists of 2 things:
- * 1) Updating the resource descriptor and dirtying it.
- * 2) Adding a relocation to the CS, so that it's usable.
- */
-
- /* Vertex buffers. */
- if (rbuffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
- for (i = 0; i < num_elems; i++) {
- int vb = sctx->vertex_elements->vertex_buffer_index[i];
-
- if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
- continue;
- if (!sctx->vertex_buffer[vb].buffer.resource)
- continue;
-
- if (sctx->vertex_buffer[vb].buffer.resource == buf) {
- sctx->vertex_buffers_dirty = true;
- break;
- }
- }
- }
-
- /* Streamout buffers. (other internal buffers can't be invalidated) */
- if (rbuffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
- for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
- struct si_buffer_resources *buffers = &sctx->rw_buffers;
- struct si_descriptors *descs =
- &sctx->descriptors[SI_DESCS_RW_BUFFERS];
-
- if (buffers->buffers[i] != buf)
- continue;
-
- si_desc_reset_buffer_offset(ctx, descs->list + i*4,
- old_va, buf);
- sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
-
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- rbuffer, buffers->shader_usage,
- RADEON_PRIO_SHADER_RW_BUFFER,
- true);
-
- /* Update the streamout state. */
- if (sctx->streamout.begin_emitted)
- si_emit_streamout_end(sctx);
- sctx->streamout.append_bitmask =
- sctx->streamout.enabled_mask;
- si_streamout_buffers_dirty(sctx);
- }
- }
-
- /* Constant and shader buffers. */
- if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
- for (shader = 0; shader < SI_NUM_SHADERS; shader++)
- si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
- si_const_and_shader_buffer_descriptors_idx(shader),
- u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS),
- buf, old_va,
- sctx->const_and_shader_buffers[shader].shader_usage_constbuf,
- sctx->const_and_shader_buffers[shader].priority_constbuf);
- }
-
- if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
- for (shader = 0; shader < SI_NUM_SHADERS; shader++)
- si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
- si_const_and_shader_buffer_descriptors_idx(shader),
- u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS),
- buf, old_va,
- sctx->const_and_shader_buffers[shader].shader_usage,
- sctx->const_and_shader_buffers[shader].priority);
- }
-
- if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
- /* Texture buffers - update bindings. */
- for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
- struct si_samplers *samplers = &sctx->samplers[shader];
- struct si_descriptors *descs =
- si_sampler_and_image_descriptors(sctx, shader);
- unsigned mask = samplers->enabled_mask;
-
- while (mask) {
- unsigned i = u_bit_scan(&mask);
- if (samplers->views[i]->texture == buf) {
- unsigned desc_slot = si_get_sampler_slot(i);
-
- si_desc_reset_buffer_offset(ctx,
- descs->list +
- desc_slot * 16 + 4,
- old_va, buf);
- sctx->descriptors_dirty |=
- 1u << si_sampler_and_image_descriptors_idx(shader);
-
- radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
- rbuffer, RADEON_USAGE_READ,
- RADEON_PRIO_SAMPLER_BUFFER,
- true);
- }
- }
- }
- }
-
- /* Shader images */
- if (rbuffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
- for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
- struct si_images *images = &sctx->images[shader];
- struct si_descriptors *descs =
- si_sampler_and_image_descriptors(sctx, shader);
- unsigned mask = images->enabled_mask;
-
- while (mask) {
- unsigned i = u_bit_scan(&mask);
-
- if (images->views[i].resource == buf) {
- unsigned desc_slot = si_get_image_slot(i);
-
- if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
- si_mark_image_range_valid(&images->views[i]);
-
- si_desc_reset_buffer_offset(
- ctx, descs->list + desc_slot * 8 + 4,
- old_va, buf);
- sctx->descriptors_dirty |=
- 1u << si_sampler_and_image_descriptors_idx(shader);
-
- radeon_add_to_buffer_list_check_mem(
- &sctx->b, &sctx->b.gfx, rbuffer,
- RADEON_USAGE_READWRITE,
- RADEON_PRIO_SAMPLER_BUFFER, true);
- }
- }
- }
- }
-
- /* Bindless texture handles */
- if (rbuffer->texture_handle_allocated) {
- struct si_descriptors *descs = &sctx->bindless_descriptors;
-
- util_dynarray_foreach(&sctx->resident_tex_handles,
- struct si_texture_handle *, tex_handle) {
- struct pipe_sampler_view *view = (*tex_handle)->view;
- unsigned desc_slot = (*tex_handle)->desc_slot;
-
- if (view->texture == buf) {
- si_set_buf_desc_address(rbuffer,
- view->u.buf.offset,
- descs->list +
- desc_slot * 16 + 4);
-
- (*tex_handle)->desc_dirty = true;
- sctx->bindless_descriptors_dirty = true;
-
- radeon_add_to_buffer_list_check_mem(
- &sctx->b, &sctx->b.gfx, rbuffer,
- RADEON_USAGE_READ,
- RADEON_PRIO_SAMPLER_BUFFER, true);
- }
- }
- }
-
- /* Bindless image handles */
- if (rbuffer->image_handle_allocated) {
- struct si_descriptors *descs = &sctx->bindless_descriptors;
-
- util_dynarray_foreach(&sctx->resident_img_handles,
- struct si_image_handle *, img_handle) {
- struct pipe_image_view *view = &(*img_handle)->view;
- unsigned desc_slot = (*img_handle)->desc_slot;
-
- if (view->resource == buf) {
- if (view->access & PIPE_IMAGE_ACCESS_WRITE)
- si_mark_image_range_valid(view);
-
- si_set_buf_desc_address(rbuffer,
- view->u.buf.offset,
- descs->list +
- desc_slot * 16 + 4);
-
- (*img_handle)->desc_dirty = true;
- sctx->bindless_descriptors_dirty = true;
-
- radeon_add_to_buffer_list_check_mem(
- &sctx->b, &sctx->b.gfx, rbuffer,
- RADEON_USAGE_READWRITE,
- RADEON_PRIO_SAMPLER_BUFFER, true);
- }
- }
- }
-}
-
-/* Reallocate a buffer a update all resource bindings where the buffer is
- * bound.
- *
- * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
- * idle by discarding its contents. Apps usually tell us when to do this using
- * map_buffer flags, for example.