+ }
+
+ res = (struct r600_resource *)view->resource;
+
+ if (&images->views[slot] != view)
+ util_copy_image_view(&images->views[slot], view);
+
+ if (res->b.b.target == PIPE_BUFFER) {
+ if (view->access & PIPE_IMAGE_ACCESS_WRITE)
+ si_mark_image_range_valid(view);
+
+ si_make_buffer_descriptor(screen, res,
+ view->format,
+ view->u.buf.offset,
+ view->u.buf.size, desc);
+ si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
+
+ images->compressed_colortex_mask &= ~(1 << slot);
+ res->bind_history |= PIPE_BIND_SHADER_IMAGE;
+ } else {
+ static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
+ struct r600_texture *tex = (struct r600_texture *)res;
+ unsigned level = view->u.tex.level;
+ unsigned width, height, depth, hw_level;
+ bool uses_dcc = vi_dcc_enabled(tex, level);
+
+ assert(!tex->is_depth);
+ assert(tex->fmask.size == 0);
+
+ if (uses_dcc && !skip_decompress &&
+ (view->access & PIPE_IMAGE_ACCESS_WRITE ||
+ !vi_dcc_formats_compatible(res->b.b.format, view->format))) {
+ /* If DCC can't be disabled, at least decompress it.
+ * The decompression is relatively cheap if the surface
+ * has been decompressed already.
+ */
+ if (r600_texture_disable_dcc(&ctx->b, tex))
+ uses_dcc = false;
+ else
+ ctx->b.decompress_dcc(&ctx->b.b, tex);
+ }
+
+ if (is_compressed_colortex(tex)) {
+ images->compressed_colortex_mask |= 1 << slot;
+ } else {
+ images->compressed_colortex_mask &= ~(1 << slot);
+ }
+
+ if (uses_dcc &&
+ p_atomic_read(&tex->framebuffers_bound))
+ ctx->need_check_render_feedback = true;
+
+ if (ctx->b.chip_class >= GFX9) {
+ /* Always set the base address. The swizzle modes don't
+ * allow setting mipmap level offsets as the base.
+ */
+ width = res->b.b.width0;
+ height = res->b.b.height0;
+ depth = res->b.b.depth0;
+ hw_level = level;
+ } else {
+ /* Always force the base level to the selected level.
+ *
+ * This is required for 3D textures, where otherwise
+ * selecting a single slice for non-layered bindings
+ * fails. It doesn't hurt the other targets.
+ */
+ width = u_minify(res->b.b.width0, level);
+ height = u_minify(res->b.b.height0, level);
+ depth = u_minify(res->b.b.depth0, level);
+ hw_level = 0;
+ }
+
+ si_make_texture_descriptor(screen, tex,
+ false, res->b.b.target,
+ view->format, swizzle,
+ hw_level, hw_level,
+ view->u.tex.first_layer,
+ view->u.tex.last_layer,
+ width, height, depth,
+ desc, NULL);
+ si_set_mutable_tex_desc_fields(screen, tex,
+ &tex->surface.u.legacy.level[level],
+ level, level,
+ util_format_get_blockwidth(view->format),
+ false, desc);
+ }
+
+ images->enabled_mask |= 1u << slot;
+ /* two 8-byte images share one 16-byte slot */
+ descs->dirty_mask |= 1u << (desc_slot / 2);
+ ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
+
+ /* Since this can flush, it must be done after enabled_mask is updated. */
+ si_sampler_view_add_buffer(ctx, &res->b.b,
+ RADEON_USAGE_READWRITE, false, true);
+}
+
+static void
+si_set_shader_images(struct pipe_context *pipe,
+ enum pipe_shader_type shader,
+ unsigned start_slot, unsigned count,
+ const struct pipe_image_view *views)
+{
+ struct si_context *ctx = (struct si_context *)pipe;
+ unsigned i, slot;
+
+ assert(shader < SI_NUM_SHADERS);
+
+ if (!count)
+ return;
+
+ assert(start_slot + count <= SI_NUM_IMAGES);
+
+ if (views) {
+ for (i = 0, slot = start_slot; i < count; ++i, ++slot)
+ si_set_shader_image(ctx, shader, slot, &views[i], false);
+ } else {
+ for (i = 0, slot = start_slot; i < count; ++i, ++slot)
+ si_set_shader_image(ctx, shader, slot, NULL, false);
+ }
+
+ si_update_compressed_tex_shader_mask(ctx, shader);
+}
+
+static void
+si_images_update_compressed_colortex_mask(struct si_images_info *images)
+{
+ unsigned mask = images->enabled_mask;
+
+ while (mask) {
+ int i = u_bit_scan(&mask);
+ struct pipe_resource *res = images->views[i].resource;
+
+ if (res && res->target != PIPE_BUFFER) {
+ struct r600_texture *rtex = (struct r600_texture *)res;
+
+ if (is_compressed_colortex(rtex)) {
+ images->compressed_colortex_mask |= 1 << i;
+ } else {
+ images->compressed_colortex_mask &= ~(1 << i);
+ }
+ }
+ }