- struct si_pc_block_base *regs = block->b->b;
- struct radeon_cmdbuf *cs = sctx->gfx_cs;
- unsigned idx;
- unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
- unsigned dw;
-
- assert(count <= regs->num_counters);
-
- if (regs->layout & SI_PC_FAKE)
- return;
-
- if (layout_multi == SI_PC_MULTI_BLOCK) {
- assert(!(regs->layout & SI_PC_REG_REVERSE));
-
- dw = count + regs->num_prelude;
- if (count >= regs->num_multi)
- dw += regs->num_multi;
- radeon_set_uconfig_reg_seq(cs, regs->select0, dw);
- for (idx = 0; idx < regs->num_prelude; ++idx)
- radeon_emit(cs, 0);
- for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
- radeon_emit(cs, selectors[idx] | regs->select_or);
-
- if (count < regs->num_multi) {
- unsigned select1 =
- regs->select0 + 4 * regs->num_multi;
- radeon_set_uconfig_reg_seq(cs, select1, count);
- }
-
- for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
- radeon_emit(cs, 0);
-
- if (count > regs->num_multi) {
- for (idx = regs->num_multi; idx < count; ++idx)
- radeon_emit(cs, selectors[idx] | regs->select_or);
- }
- } else if (layout_multi == SI_PC_MULTI_TAIL) {
- unsigned select1, select1_count;
-
- assert(!(regs->layout & SI_PC_REG_REVERSE));
-
- radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude);
- for (idx = 0; idx < regs->num_prelude; ++idx)
- radeon_emit(cs, 0);
- for (idx = 0; idx < count; ++idx)
- radeon_emit(cs, selectors[idx] | regs->select_or);
-
- select1 = regs->select0 + 4 * regs->num_counters;
- select1_count = MIN2(count, regs->num_multi);
- radeon_set_uconfig_reg_seq(cs, select1, select1_count);
- for (idx = 0; idx < select1_count; ++idx)
- radeon_emit(cs, 0);
- } else if (layout_multi == SI_PC_MULTI_CUSTOM) {
- unsigned *reg = regs->select;
- for (idx = 0; idx < count; ++idx) {
- radeon_set_uconfig_reg(cs, *reg++, selectors[idx] | regs->select_or);
- if (idx < regs->num_multi)
- radeon_set_uconfig_reg(cs, *reg++, 0);
- }
- } else {
- assert(layout_multi == SI_PC_MULTI_ALTERNATE);
-
- unsigned reg_base = regs->select0;
- unsigned reg_count = count + MIN2(count, regs->num_multi);
- reg_count += regs->num_prelude;
-
- if (!(regs->layout & SI_PC_REG_REVERSE)) {
- radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
-
- for (idx = 0; idx < regs->num_prelude; ++idx)
- radeon_emit(cs, 0);
- for (idx = 0; idx < count; ++idx) {
- radeon_emit(cs, selectors[idx] | regs->select_or);
- if (idx < regs->num_multi)
- radeon_emit(cs, 0);
- }
- } else {
- reg_base -= (reg_count - 1) * 4;
- radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
-
- for (idx = count; idx > 0; --idx) {
- if (idx <= regs->num_multi)
- radeon_emit(cs, 0);
- radeon_emit(cs, selectors[idx - 1] | regs->select_or);
- }
- for (idx = 0; idx < regs->num_prelude; ++idx)
- radeon_emit(cs, 0);
- }
- }
+ struct si_pc_block_base *regs = block->b->b;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
+ unsigned idx;
+ unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
+ unsigned dw;
+
+ assert(count <= regs->num_counters);
+
+ if (regs->layout & SI_PC_FAKE)
+ return;
+
+ if (layout_multi == SI_PC_MULTI_BLOCK) {
+ assert(!(regs->layout & SI_PC_REG_REVERSE));
+
+ dw = count + regs->num_prelude;
+ if (count >= regs->num_multi)
+ dw += regs->num_multi;
+ radeon_set_uconfig_reg_seq(cs, regs->select0, dw);
+ for (idx = 0; idx < regs->num_prelude; ++idx)
+ radeon_emit(cs, 0);
+ for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
+ radeon_emit(cs, selectors[idx] | regs->select_or);
+
+ if (count < regs->num_multi) {
+ unsigned select1 = regs->select0 + 4 * regs->num_multi;
+ radeon_set_uconfig_reg_seq(cs, select1, count);
+ }
+
+ for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
+ radeon_emit(cs, 0);
+
+ if (count > regs->num_multi) {
+ for (idx = regs->num_multi; idx < count; ++idx)
+ radeon_emit(cs, selectors[idx] | regs->select_or);
+ }
+ } else if (layout_multi == SI_PC_MULTI_TAIL) {
+ unsigned select1, select1_count;
+
+ assert(!(regs->layout & SI_PC_REG_REVERSE));
+
+ radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude);
+ for (idx = 0; idx < regs->num_prelude; ++idx)
+ radeon_emit(cs, 0);
+ for (idx = 0; idx < count; ++idx)
+ radeon_emit(cs, selectors[idx] | regs->select_or);
+
+ select1 = regs->select0 + 4 * regs->num_counters;
+ select1_count = MIN2(count, regs->num_multi);
+ radeon_set_uconfig_reg_seq(cs, select1, select1_count);
+ for (idx = 0; idx < select1_count; ++idx)
+ radeon_emit(cs, 0);
+ } else if (layout_multi == SI_PC_MULTI_CUSTOM) {
+ unsigned *reg = regs->select;
+ for (idx = 0; idx < count; ++idx) {
+ radeon_set_uconfig_reg(cs, *reg++, selectors[idx] | regs->select_or);
+ if (idx < regs->num_multi)
+ radeon_set_uconfig_reg(cs, *reg++, 0);
+ }
+ } else {
+ assert(layout_multi == SI_PC_MULTI_ALTERNATE);
+
+ unsigned reg_base = regs->select0;
+ unsigned reg_count = count + MIN2(count, regs->num_multi);
+ reg_count += regs->num_prelude;
+
+ if (!(regs->layout & SI_PC_REG_REVERSE)) {
+ radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
+
+ for (idx = 0; idx < regs->num_prelude; ++idx)
+ radeon_emit(cs, 0);
+ for (idx = 0; idx < count; ++idx) {
+ radeon_emit(cs, selectors[idx] | regs->select_or);
+ if (idx < regs->num_multi)
+ radeon_emit(cs, 0);
+ }
+ } else {
+ reg_base -= (reg_count - 1) * 4;
+ radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
+
+ for (idx = count; idx > 0; --idx) {
+ if (idx <= regs->num_multi)
+ radeon_emit(cs, 0);
+ radeon_emit(cs, selectors[idx - 1] | regs->select_or);
+ }
+ for (idx = 0; idx < regs->num_prelude; ++idx)
+ radeon_emit(cs, 0);
+ }
+ }