- struct pipe_context b; /* base class */
-
- enum radeon_family family;
- enum chip_class chip_class;
-
- struct radeon_winsys *ws;
- struct radeon_winsys_ctx *ctx;
- struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
- struct radeon_cmdbuf *dma_cs;
- struct pipe_fence_handle *last_gfx_fence;
- struct pipe_fence_handle *last_sdma_fence;
- struct si_resource *eop_bug_scratch;
- struct u_upload_mgr *cached_gtt_allocator;
- struct threaded_context *tc;
- struct u_suballocator *allocator_zeroed_memory;
- struct slab_child_pool pool_transfers;
- struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
- struct pipe_device_reset_callback device_reset_callback;
- struct u_log_context *log;
- void *query_result_shader;
- struct blitter_context *blitter;
- void *custom_dsa_flush;
- void *custom_blend_resolve;
- void *custom_blend_fmask_decompress;
- void *custom_blend_eliminate_fastclear;
- void *custom_blend_dcc_decompress;
- void *vs_blit_pos;
- void *vs_blit_pos_layered;
- void *vs_blit_color;
- void *vs_blit_color_layered;
- void *vs_blit_texcoord;
- void *cs_clear_buffer;
- void *cs_copy_buffer;
- void *cs_copy_image;
- void *cs_copy_image_1d_array;
- void *cs_clear_render_target;
- void *cs_clear_render_target_1d_array;
- void *cs_dcc_retile;
- struct si_screen *screen;
- struct pipe_debug_callback debug;
- struct ac_llvm_compiler compiler; /* only non-threaded compilation */
- struct si_shader_ctx_state fixed_func_tcs_shader;
- struct si_resource *wait_mem_scratch;
- unsigned wait_mem_number;
- uint16_t prefetch_L2_mask;
-
- bool has_graphics;
- bool gfx_flush_in_progress:1;
- bool gfx_last_ib_is_busy:1;
- bool compute_is_busy:1;
-
- unsigned num_gfx_cs_flushes;
- unsigned initial_gfx_cs_size;
- unsigned gpu_reset_counter;
- unsigned last_dirty_tex_counter;
- unsigned last_compressed_colortex_counter;
- unsigned last_num_draw_calls;
- unsigned flags; /* flush flags */
- /* Current unaccounted memory usage. */
- uint64_t vram;
- uint64_t gtt;
-
- /* Atoms (direct states). */
- union si_state_atoms atoms;
- unsigned dirty_atoms; /* mask */
- /* PM4 states (precomputed immutable states) */
- unsigned dirty_states;
- union si_state queued;
- union si_state emitted;
-
- /* Atom declarations. */
- struct si_framebuffer framebuffer;
- unsigned sample_locs_num_samples;
- uint16_t sample_mask;
- unsigned last_cb_target_mask;
- struct si_blend_color blend_color;
- struct si_clip_state clip_state;
- struct si_shader_data shader_pointers;
- struct si_stencil_ref stencil_ref;
- struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
- struct si_streamout streamout;
- struct si_viewports viewports;
- unsigned num_window_rectangles;
- bool window_rectangles_include;
- struct pipe_scissor_state window_rectangles[4];
-
- /* Precomputed states. */
- struct si_pm4_state *init_config;
- struct si_pm4_state *init_config_gs_rings;
- bool init_config_has_vgt_flush;
- struct si_pm4_state *vgt_shader_config[4];
-
- /* shaders */
- struct si_shader_ctx_state ps_shader;
- struct si_shader_ctx_state gs_shader;
- struct si_shader_ctx_state vs_shader;
- struct si_shader_ctx_state tcs_shader;
- struct si_shader_ctx_state tes_shader;
- struct si_cs_shader_state cs_shader_state;
-
- /* shader information */
- struct si_vertex_elements *vertex_elements;
- unsigned sprite_coord_enable;
- unsigned cs_max_waves_per_sh;
- bool flatshade;
- bool do_update_shaders;
-
- /* vertex buffer descriptors */
- uint32_t *vb_descriptors_gpu_list;
- struct si_resource *vb_descriptors_buffer;
- unsigned vb_descriptors_offset;
-
- /* shader descriptors */
- struct si_descriptors descriptors[SI_NUM_DESCS];
- unsigned descriptors_dirty;
- unsigned shader_pointers_dirty;
- unsigned shader_needs_decompress_mask;
- struct si_buffer_resources rw_buffers;
- struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
- struct si_samplers samplers[SI_NUM_SHADERS];
- struct si_images images[SI_NUM_SHADERS];
- bool bo_list_add_all_resident_resources;
- bool bo_list_add_all_gfx_resources;
- bool bo_list_add_all_compute_resources;
-
- /* other shader resources */
- struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
- struct pipe_resource *esgs_ring;
- struct pipe_resource *gsvs_ring;
- struct pipe_resource *tess_rings;
- union pipe_color_union *border_color_table; /* in CPU memory, any endian */
- struct si_resource *border_color_buffer;
- union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
- unsigned border_color_count;
- unsigned num_vs_blit_sgprs;
- uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
- uint32_t cs_user_data[4];
-
- /* Vertex and index buffers. */
- bool vertex_buffers_dirty;
- bool vertex_buffer_pointer_dirty;
- struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
- uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
-
- /* MSAA config state. */
- int ps_iter_samples;
- bool ps_uses_fbfetch;
- bool smoothing_enabled;
-
- /* DB render state. */
- unsigned ps_db_shader_control;
- unsigned dbcb_copy_sample;
- bool dbcb_depth_copy_enabled:1;
- bool dbcb_stencil_copy_enabled:1;
- bool db_flush_depth_inplace:1;
- bool db_flush_stencil_inplace:1;
- bool db_depth_clear:1;
- bool db_depth_disable_expclear:1;
- bool db_stencil_clear:1;
- bool db_stencil_disable_expclear:1;
- bool occlusion_queries_disabled:1;
- bool generate_mipmap_for_depth:1;
-
- /* Emitted draw state. */
- bool gs_tri_strip_adj_fix:1;
- bool ls_vgpr_fix:1;
- int last_index_size;
- int last_base_vertex;
- int last_start_instance;
- int last_instance_count;
- int last_drawid;
- int last_sh_base_reg;
- int last_primitive_restart_en;
- int last_restart_index;
- int last_prim;
- int last_multi_vgt_param;
- int last_rast_prim;
- unsigned last_sc_line_stipple;
- unsigned current_vs_state;
- unsigned last_vs_state;
- enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
-
- /* Scratch buffer */
- struct si_resource *scratch_buffer;
- unsigned scratch_waves;
- unsigned spi_tmpring_size;
-
- struct si_resource *compute_scratch_buffer;
-
- /* Emitted derived tessellation state. */
- /* Local shader (VS), or HS if LS-HS are merged. */
- struct si_shader *last_ls;
- struct si_shader_selector *last_tcs;
- int last_num_tcs_input_cp;
- int last_tes_sh_base;
- bool last_tess_uses_primid;
- unsigned last_num_patches;
- int last_ls_hs_config;
-
- /* Debug state. */
- bool is_debug;
- struct si_saved_cs *current_saved_cs;
- uint64_t dmesg_timestamp;
- unsigned apitrace_call_number;
-
- /* Other state */
- bool need_check_render_feedback;
- bool decompression_enabled;
- bool dpbb_force_off;
- bool vs_writes_viewport_index;
- bool vs_disables_clipping_viewport;
-
- /* Precomputed IA_MULTI_VGT_PARAM */
- union si_vgt_param_key ia_multi_vgt_param_key;
- unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
-
- /* Bindless descriptors. */
- struct si_descriptors bindless_descriptors;
- struct util_idalloc bindless_used_slots;
- unsigned num_bindless_descriptors;
- bool bindless_descriptors_dirty;
- bool graphics_bindless_pointer_dirty;
- bool compute_bindless_pointer_dirty;
-
- /* Allocated bindless handles */
- struct hash_table *tex_handles;
- struct hash_table *img_handles;
-
- /* Resident bindless handles */
- struct util_dynarray resident_tex_handles;
- struct util_dynarray resident_img_handles;
-
- /* Resident bindless handles which need decompression */
- struct util_dynarray resident_tex_needs_color_decompress;
- struct util_dynarray resident_img_needs_color_decompress;
- struct util_dynarray resident_tex_needs_depth_decompress;
-
- /* Bindless state */
- bool uses_bindless_samplers;
- bool uses_bindless_images;
-
- /* MSAA sample locations.
- * The first index is the sample index.
- * The second index is the coordinate: X, Y. */
- struct {
- float x1[1][2];
- float x2[2][2];
- float x4[4][2];
- float x8[8][2];
- float x16[16][2];
- } sample_positions;
- struct pipe_resource *sample_pos_buffer;
-
- /* Misc stats. */
- unsigned num_draw_calls;
- unsigned num_decompress_calls;
- unsigned num_mrt_draw_calls;
- unsigned num_prim_restart_calls;
- unsigned num_spill_draw_calls;
- unsigned num_compute_calls;
- unsigned num_spill_compute_calls;
- unsigned num_dma_calls;
- unsigned num_cp_dma_calls;
- unsigned num_vs_flushes;
- unsigned num_ps_flushes;
- unsigned num_cs_flushes;
- unsigned num_cb_cache_flushes;
- unsigned num_db_cache_flushes;
- unsigned num_L2_invalidates;
- unsigned num_L2_writebacks;
- unsigned num_resident_handles;
- uint64_t num_alloc_tex_transfer_bytes;
- unsigned last_tex_ps_draw_ratio; /* for query */
- unsigned context_roll;
-
- /* Queries. */
- /* Maintain the list of active queries for pausing between IBs. */
- int num_occlusion_queries;
- int num_perfect_occlusion_queries;
- struct list_head active_queries;
- unsigned num_cs_dw_queries_suspend;
-
- /* Render condition. */
- struct pipe_query *render_cond;
- unsigned render_cond_mode;
- bool render_cond_invert;
- bool render_cond_force_off; /* for u_blitter */
-
- /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
- bool sdma_uploads_in_progress;
- struct si_sdma_upload *sdma_uploads;
- unsigned num_sdma_uploads;
- unsigned max_sdma_uploads;
-
- /* Statistics gathering for the DCC enablement heuristic. It can't be
- * in si_texture because si_texture can be shared by multiple
- * contexts. This is for back buffers only. We shouldn't get too many
- * of those.
- *
- * X11 DRI3 rotates among a finite set of back buffers. They should
- * all fit in this array. If they don't, separate DCC might never be
- * enabled by DCC stat gathering.
- */
- struct {
- struct si_texture *tex;
- /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
- struct pipe_query *ps_stats[3];
- /* If all slots are used and another slot is needed,
- * the least recently used slot is evicted based on this. */
- int64_t last_use_timestamp;
- bool query_active;
- } dcc_stats[5];
-
- /* Copy one resource to another using async DMA. */
- void (*dma_copy)(struct pipe_context *ctx,
- struct pipe_resource *dst,
- unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src,
- unsigned src_level,
- const struct pipe_box *src_box);
-
- struct si_tracked_regs tracked_regs;
+ struct pipe_context b; /* base class */
+
+ enum radeon_family family;
+ enum chip_class chip_class;
+
+ struct radeon_winsys *ws;
+ struct radeon_winsys_ctx *ctx;
+ struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
+ struct radeon_cmdbuf *sdma_cs;
+ struct pipe_fence_handle *last_gfx_fence;
+ struct pipe_fence_handle *last_sdma_fence;
+ struct si_resource *eop_bug_scratch;
+ struct u_upload_mgr *cached_gtt_allocator;
+ struct threaded_context *tc;
+ struct u_suballocator *allocator_zeroed_memory;
+ struct slab_child_pool pool_transfers;
+ struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
+ struct pipe_device_reset_callback device_reset_callback;
+ struct u_log_context *log;
+ void *query_result_shader;
+ void *sh_query_result_shader;
+
+ void (*emit_cache_flush)(struct si_context *ctx);
+
+ struct blitter_context *blitter;
+ void *noop_blend;
+ void *noop_dsa;
+ void *discard_rasterizer_state;
+ void *custom_dsa_flush;
+ void *custom_blend_resolve;
+ void *custom_blend_fmask_decompress;
+ void *custom_blend_eliminate_fastclear;
+ void *custom_blend_dcc_decompress;
+ void *vs_blit_pos;
+ void *vs_blit_pos_layered;
+ void *vs_blit_color;
+ void *vs_blit_color_layered;
+ void *vs_blit_texcoord;
+ void *cs_clear_buffer;
+ void *cs_copy_buffer;
+ void *cs_copy_image;
+ void *cs_copy_image_1d_array;
+ void *cs_clear_render_target;
+ void *cs_clear_render_target_1d_array;
+ void *cs_clear_12bytes_buffer;
+ void *cs_dcc_decompress;
+ void *cs_dcc_retile;
+ void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
+ struct si_screen *screen;
+ struct pipe_debug_callback debug;
+ struct ac_llvm_compiler compiler; /* only non-threaded compilation */
+ struct si_shader_ctx_state fixed_func_tcs_shader;
+ /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
+ struct si_resource *wait_mem_scratch;
+ unsigned wait_mem_number;
+ uint16_t prefetch_L2_mask;
+
+ bool has_graphics;
+ bool gfx_flush_in_progress : 1;
+ bool gfx_last_ib_is_busy : 1;
+ bool compute_is_busy : 1;
+
+ unsigned num_gfx_cs_flushes;
+ unsigned initial_gfx_cs_size;
+ unsigned last_dirty_tex_counter;
+ unsigned last_dirty_buf_counter;
+ unsigned last_compressed_colortex_counter;
+ unsigned last_num_draw_calls;
+ unsigned flags; /* flush flags */
+ /* Current unaccounted memory usage. */
+ uint64_t vram;
+ uint64_t gtt;
+
+ /* Compute-based primitive discard. */
+ unsigned prim_discard_vertex_count_threshold;
+ struct pb_buffer *gds;
+ struct pb_buffer *gds_oa;
+ struct radeon_cmdbuf *prim_discard_compute_cs;
+ unsigned compute_gds_offset;
+ struct si_shader *compute_ib_last_shader;
+ uint32_t compute_rewind_va;
+ unsigned compute_num_prims_in_batch;
+ bool preserve_prim_restart_gds_at_flush;
+ /* index_ring is divided into 2 halves for doublebuffering. */
+ struct si_resource *index_ring;
+ unsigned index_ring_base; /* offset of a per-IB portion */
+ unsigned index_ring_offset; /* offset within a per-IB portion */
+ unsigned index_ring_size_per_ib; /* max available size per IB */
+ bool prim_discard_compute_ib_initialized;
+ /* For tracking the last execution barrier - it can be either
+ * a WRITE_DATA packet or a fence. */
+ uint32_t *last_pkt3_write_data;
+ struct si_resource *barrier_buf;
+ unsigned barrier_buf_offset;
+ struct pipe_fence_handle *last_ib_barrier_fence;
+ struct si_resource *last_ib_barrier_buf;
+ unsigned last_ib_barrier_buf_offset;
+
+ /* Atoms (direct states). */
+ union si_state_atoms atoms;
+ unsigned dirty_atoms; /* mask */
+ /* PM4 states (precomputed immutable states) */
+ unsigned dirty_states;
+ union si_state queued;
+ union si_state emitted;
+
+ /* Atom declarations. */
+ struct si_framebuffer framebuffer;
+ unsigned sample_locs_num_samples;
+ uint16_t sample_mask;
+ unsigned last_cb_target_mask;
+ struct si_blend_color blend_color;
+ struct si_clip_state clip_state;
+ struct si_shader_data shader_pointers;
+ struct si_stencil_ref stencil_ref;
+ struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
+ struct si_streamout streamout;
+ struct si_viewports viewports;
+ unsigned num_window_rectangles;
+ bool window_rectangles_include;
+ struct pipe_scissor_state window_rectangles[4];
+
+ /* Precomputed states. */
+ struct si_pm4_state *init_config;
+ struct si_pm4_state *init_config_gs_rings;
+ bool init_config_has_vgt_flush;
+ struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
+
+ /* shaders */
+ struct si_shader_ctx_state ps_shader;
+ struct si_shader_ctx_state gs_shader;
+ struct si_shader_ctx_state vs_shader;
+ struct si_shader_ctx_state tcs_shader;
+ struct si_shader_ctx_state tes_shader;
+ struct si_shader_ctx_state cs_prim_discard_state;
+ struct si_cs_shader_state cs_shader_state;
+
+ /* shader information */
+ struct si_vertex_elements *vertex_elements;
+ unsigned num_vertex_elements;
+ unsigned sprite_coord_enable;
+ unsigned cs_max_waves_per_sh;
+ bool flatshade;
+ bool do_update_shaders;
+
+ /* shader descriptors */
+ struct si_descriptors descriptors[SI_NUM_DESCS];
+ unsigned descriptors_dirty;
+ unsigned shader_pointers_dirty;
+ unsigned shader_needs_decompress_mask;
+ struct si_buffer_resources rw_buffers;
+ struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
+ struct si_samplers samplers[SI_NUM_SHADERS];
+ struct si_images images[SI_NUM_SHADERS];
+ bool bo_list_add_all_resident_resources;
+ bool bo_list_add_all_gfx_resources;
+ bool bo_list_add_all_compute_resources;
+
+ /* other shader resources */
+ struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
+ struct pipe_resource *esgs_ring;
+ struct pipe_resource *gsvs_ring;
+ struct pipe_resource *tess_rings;
+ union pipe_color_union *border_color_table; /* in CPU memory, any endian */
+ struct si_resource *border_color_buffer;
+ union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
+ unsigned border_color_count;
+ unsigned num_vs_blit_sgprs;
+ uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
+ uint32_t cs_user_data[4];
+
+ /* Vertex buffers. */
+ bool vertex_buffers_dirty;
+ bool vertex_buffer_pointer_dirty;
+ bool vertex_buffer_user_sgprs_dirty;
+ struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
+ uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
+ uint32_t *vb_descriptors_gpu_list;
+ struct si_resource *vb_descriptors_buffer;
+ unsigned vb_descriptors_offset;
+ unsigned vb_descriptor_user_sgprs[5 * 4];
+
+ /* MSAA config state. */
+ int ps_iter_samples;
+ bool ps_uses_fbfetch;
+ bool smoothing_enabled;
+
+ /* DB render state. */
+ unsigned ps_db_shader_control;
+ unsigned dbcb_copy_sample;
+ bool dbcb_depth_copy_enabled : 1;
+ bool dbcb_stencil_copy_enabled : 1;
+ bool db_flush_depth_inplace : 1;
+ bool db_flush_stencil_inplace : 1;
+ bool db_depth_clear : 1;
+ bool db_depth_disable_expclear : 1;
+ bool db_stencil_clear : 1;
+ bool db_stencil_disable_expclear : 1;
+ bool occlusion_queries_disabled : 1;
+ bool generate_mipmap_for_depth : 1;
+
+ /* Emitted draw state. */
+ bool gs_tri_strip_adj_fix : 1;
+ bool ls_vgpr_fix : 1;
+ bool prim_discard_cs_instancing : 1;
+ bool ngg : 1;
+ uint8_t ngg_culling;
+ int last_index_size;
+ int last_base_vertex;
+ int last_start_instance;
+ int last_instance_count;
+ int last_drawid;
+ int last_sh_base_reg;
+ int last_primitive_restart_en;
+ int last_restart_index;
+ int last_prim;
+ int last_multi_vgt_param;
+ int last_gs_out_prim;
+ int last_binning_enabled;
+ unsigned current_vs_state;
+ unsigned last_vs_state;
+ enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
+
+ struct si_small_prim_cull_info last_small_prim_cull_info;
+ struct si_resource *small_prim_cull_info_buf;
+ uint64_t small_prim_cull_info_address;
+ bool small_prim_cull_info_dirty;
+
+ /* Scratch buffer */
+ struct si_resource *scratch_buffer;
+ unsigned scratch_waves;
+ unsigned spi_tmpring_size;
+ unsigned max_seen_scratch_bytes_per_wave;
+ unsigned max_seen_compute_scratch_bytes_per_wave;
+
+ struct si_resource *compute_scratch_buffer;
+
+ /* Emitted derived tessellation state. */
+ /* Local shader (VS), or HS if LS-HS are merged. */
+ struct si_shader *last_ls;
+ struct si_shader_selector *last_tcs;
+ int last_num_tcs_input_cp;
+ int last_tes_sh_base;
+ bool last_tess_uses_primid;
+ unsigned last_num_patches;
+ int last_ls_hs_config;
+
+ /* Debug state. */
+ bool is_debug;
+ struct si_saved_cs *current_saved_cs;
+ uint64_t dmesg_timestamp;
+ unsigned apitrace_call_number;
+
+ /* Other state */
+ bool need_check_render_feedback;
+ bool decompression_enabled;
+ bool dpbb_force_off;
+ bool vs_writes_viewport_index;
+ bool vs_disables_clipping_viewport;
+
+ /* Precomputed IA_MULTI_VGT_PARAM */
+ union si_vgt_param_key ia_multi_vgt_param_key;
+ unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
+
+ /* Bindless descriptors. */
+ struct si_descriptors bindless_descriptors;
+ struct util_idalloc bindless_used_slots;
+ unsigned num_bindless_descriptors;
+ bool bindless_descriptors_dirty;
+ bool graphics_bindless_pointer_dirty;
+ bool compute_bindless_pointer_dirty;
+
+ /* Allocated bindless handles */
+ struct hash_table *tex_handles;
+ struct hash_table *img_handles;
+
+ /* Resident bindless handles */
+ struct util_dynarray resident_tex_handles;
+ struct util_dynarray resident_img_handles;
+
+ /* Resident bindless handles which need decompression */
+ struct util_dynarray resident_tex_needs_color_decompress;
+ struct util_dynarray resident_img_needs_color_decompress;
+ struct util_dynarray resident_tex_needs_depth_decompress;
+
+ /* Bindless state */
+ bool uses_bindless_samplers;
+ bool uses_bindless_images;
+
+ /* MSAA sample locations.
+ * The first index is the sample index.
+ * The second index is the coordinate: X, Y. */
+ struct {
+ float x1[1][2];
+ float x2[2][2];
+ float x4[4][2];
+ float x8[8][2];
+ float x16[16][2];
+ } sample_positions;
+ struct pipe_resource *sample_pos_buffer;
+
+ /* Misc stats. */
+ unsigned num_draw_calls;
+ unsigned num_decompress_calls;
+ unsigned num_mrt_draw_calls;
+ unsigned num_prim_restart_calls;
+ unsigned num_spill_draw_calls;
+ unsigned num_compute_calls;
+ unsigned num_spill_compute_calls;
+ unsigned num_dma_calls;
+ unsigned num_cp_dma_calls;
+ unsigned num_vs_flushes;
+ unsigned num_ps_flushes;
+ unsigned num_cs_flushes;
+ unsigned num_cb_cache_flushes;
+ unsigned num_db_cache_flushes;
+ unsigned num_L2_invalidates;
+ unsigned num_L2_writebacks;
+ unsigned num_resident_handles;
+ uint64_t num_alloc_tex_transfer_bytes;
+ unsigned last_tex_ps_draw_ratio; /* for query */
+ unsigned compute_num_verts_accepted;
+ unsigned compute_num_verts_rejected;
+ unsigned compute_num_verts_ineligible; /* due to low vertex count */
+ unsigned context_roll;
+
+ /* Queries. */
+ /* Maintain the list of active queries for pausing between IBs. */
+ int num_occlusion_queries;
+ int num_perfect_occlusion_queries;
+ int num_pipeline_stat_queries;
+ struct list_head active_queries;
+ unsigned num_cs_dw_queries_suspend;
+
+ /* Render condition. */
+ struct pipe_query *render_cond;
+ unsigned render_cond_mode;
+ bool render_cond_invert;
+ bool render_cond_force_off; /* for u_blitter */
+
+ /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
+ bool sdma_uploads_in_progress;
+ struct si_sdma_upload *sdma_uploads;
+ unsigned num_sdma_uploads;
+ unsigned max_sdma_uploads;
+
+ /* Shader-based queries. */
+ struct list_head shader_query_buffers;
+ unsigned num_active_shader_queries;
+
+ /* Statistics gathering for the DCC enablement heuristic. It can't be
+ * in si_texture because si_texture can be shared by multiple
+ * contexts. This is for back buffers only. We shouldn't get too many
+ * of those.
+ *
+ * X11 DRI3 rotates among a finite set of back buffers. They should
+ * all fit in this array. If they don't, separate DCC might never be
+ * enabled by DCC stat gathering.
+ */
+ struct {
+ struct si_texture *tex;
+ /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
+ struct pipe_query *ps_stats[3];
+ /* If all slots are used and another slot is needed,
+ * the least recently used slot is evicted based on this. */
+ int64_t last_use_timestamp;
+ bool query_active;
+ } dcc_stats[5];
+
+ /* Copy one resource to another using async DMA. */
+ void (*dma_copy)(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dst_level,
+ unsigned dst_x, unsigned dst_y, unsigned dst_z, struct pipe_resource *src,
+ unsigned src_level, const struct pipe_box *src_box);
+
+ struct si_tracked_regs tracked_regs;