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radeonsi: enable PIPE_CAP_NO_CLIP_ON_COPY_TEX
[mesa.git]
/
src
/
gallium
/
drivers
/
radeonsi
/
si_pm4.h
diff --git
a/src/gallium/drivers/radeonsi/si_pm4.h
b/src/gallium/drivers/radeonsi/si_pm4.h
index 5bd177332ebc817e5f84544887bd5af45f81f89b..f8edea4d0cb450b15ce173a52ca15b62f262be07 100644
(file)
--- a/
src/gallium/drivers/radeonsi/si_pm4.h
+++ b/
src/gallium/drivers/radeonsi/si_pm4.h
@@
-1,5
+1,6
@@
/*
* Copyright 2012 Advanced Micro Devices, Inc.
/*
* Copyright 2012 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@
-26,51
+27,40
@@
#include "radeon/radeon_winsys.h"
#include "radeon/radeon_winsys.h"
-#define SI_PM4_MAX_DW 176
-#define SI_PM4_MAX_BO 3
+#define SI_PM4_MAX_DW 176
// forward defines
struct si_context;
// forward defines
struct si_context;
-struct si_pm4_state
-{
- /* optional indirect buffer */
- struct r600_resource *indirect_buffer;
+/* State atoms are callbacks which write a sequence of packets into a GPU
+ * command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
+ */
+struct si_atom {
+ void (*emit)(struct si_context *ctx);
+};
- /* PKT3_SET_*_REG handling */
- unsigned last_opcode;
- unsigned last_reg;
- unsigned last_pm4;
+struct si_pm4_state {
+ /* PKT3_SET_*_REG handling */
+ unsigned last_opcode;
+ unsigned last_reg;
+ unsigned last_pm4;
-
/* commands for the DE */
-
unsigned
ndw;
-
uint32_t
pm4[SI_PM4_MAX_DW];
+ /* commands for the DE */
+
unsigned
ndw;
+
uint32_t
pm4[SI_PM4_MAX_DW];
- /* BO's referenced by this state */
- unsigned nbo;
- struct r600_resource *bo[SI_PM4_MAX_BO];
- enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
- enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
+ /* For shader states only */
+ struct si_shader *shader;
+ struct si_atom atom;
};
};
-void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
-void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
-
void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
-void si_pm4_add_bo(struct si_pm4_state *state,
- struct r600_resource *bo,
- enum radeon_bo_usage usage,
- enum radeon_bo_priority priority);
-void si_pm4_upload_indirect_buffer(struct si_context *sctx,
- struct si_pm4_state *state);
void si_pm4_clear_state(struct si_pm4_state *state);
void si_pm4_clear_state(struct si_pm4_state *state);
-void si_pm4_free_state(struct si_context *sctx,
- struct si_pm4_state *state,
- unsigned idx);
+void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx);
void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
-void si_pm4_reset_emitted(struct si_context *sctx);
+void si_pm4_reset_emitted(struct si_context *sctx
, bool first_cs
);
#endif
#endif