+union si_state_atoms {
+ struct {
+ /* The order matters. */
+ struct r600_atom *cache_flush;
+ struct r600_atom *streamout_begin;
+ struct r600_atom *streamout_enable; /* must be after streamout_begin */
+ struct r600_atom *framebuffer;
+ struct r600_atom *msaa_sample_locs;
+ struct r600_atom *db_render_state;
+ struct r600_atom *msaa_config;
+ struct r600_atom *sample_mask;
+ struct r600_atom *cb_target_mask;
+ struct r600_atom *blend_color;
+ struct r600_atom *clip_regs;
+ struct r600_atom *clip_state;
+ struct r600_atom *shader_userdata;
+ struct r600_atom *scissors;
+ struct r600_atom *viewports;
+ struct r600_atom *stencil_ref;
+ struct r600_atom *spi_map;
+ struct r600_atom *spi_ps_input;
+ } s;
+ struct r600_atom *array[0];
+};
+
+#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
+
+struct si_shader_data {
+ struct r600_atom atom;
+ uint32_t sh_base[SI_NUM_SHADERS];
+};
+
+#define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
+#define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
+#define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
+
+/* User sampler views: 0..15
+ * Polygon stipple tex: 16
+ * FMASK sampler views: 17..33 (no sampler states)
+ */
+#define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS
+#define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
+#define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS
+
+/* User constant buffers: 0..15
+ * Driver state constants: 16
+ */
+#define SI_NUM_USER_CONST_BUFFERS 16
+#define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
+#define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
+
+/* Read-write buffer slots.
+ *
+ * Ring buffers: 0..1
+ * Streamout buffers: 2..5
+ */
+#define SI_RING_TESS_FACTOR 0 /* for HS (TCS) */
+#define SI_RING_ESGS 0 /* for ES, GS */
+#define SI_RING_GSVS 1 /* for GS, VS */
+#define SI_RING_GSVS_1 2 /* 1, 2, 3 for GS */
+#define SI_RING_GSVS_2 3
+#define SI_RING_GSVS_3 4
+#define SI_NUM_RING_BUFFERS 5
+#define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
+#define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
+
+#define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
+
+
+/* This represents descriptors in memory, such as buffer resources,
+ * image resources, and sampler states.
+ */
+struct si_descriptors {
+ /* The list of descriptors in malloc'd memory. */
+ uint32_t *list;
+ /* The size of one descriptor. */
+ unsigned element_dw_size;
+ /* The maximum number of descriptors. */
+ unsigned num_elements;
+ /* Whether the list has been changed and should be re-uploaded. */
+ bool list_dirty;
+
+ /* The buffer where the descriptors have been uploaded. */
+ struct r600_resource *buffer;
+ unsigned buffer_offset;
+
+ /* The i-th bit is set if that element is enabled (non-NULL resource). */
+ uint64_t enabled_mask;
+
+ /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
+ * array will be stored. */
+ unsigned shader_userdata_offset;
+ /* Whether the pointer should be re-emitted. */
+ bool pointer_dirty;
+};
+
+struct si_sampler_views {
+ struct si_descriptors desc;
+ struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS];
+};
+
+struct si_sampler_states {
+ struct si_descriptors desc;
+ void *saved_states[2]; /* saved for u_blitter */
+};
+
+struct si_buffer_resources {
+ struct si_descriptors desc;
+ enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
+ enum radeon_bo_priority priority;
+ struct pipe_resource **buffers; /* this has num_buffers elements */
+};
+