+#define NUM_TEX_UNITS 16
+
+/* User sampler views: 0..15
+ * FMASK sampler views: 16..31 (no sampler states)
+ */
+#define FMASK_TEX_OFFSET NUM_TEX_UNITS
+#define NUM_SAMPLER_VIEWS (FMASK_TEX_OFFSET+NUM_TEX_UNITS)
+#define NUM_SAMPLER_STATES NUM_TEX_UNITS
+
+#define NUM_PIPE_CONST_BUFFERS 16
+#define NUM_CONST_BUFFERS 17
+
+/* This represents resource descriptors in memory, such as buffer resources,
+ * image resources, and sampler states.
+ */
+struct si_descriptors {
+ struct r600_atom atom;
+
+ /* The size of one resource descriptor. */
+ unsigned element_dw_size;
+ /* The maximum number of resource descriptors. */
+ unsigned num_elements;
+
+ /* The buffer where resource descriptors are stored. */
+ struct r600_resource *buffer;
+
+ /* The i-th bit is set if that element is dirty (changed but not emitted). */
+ unsigned dirty_mask;
+ /* The i-th bit is set if that element is enabled (non-NULL resource). */
+ unsigned enabled_mask;
+
+ /* We can't update descriptors directly because the GPU might be
+ * reading them at the same time, so we have to update them
+ * in a copy-on-write manner. Each such copy is called a context,
+ * which is just another array descriptors in the same buffer. */
+ unsigned current_context_id;
+ /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
+ unsigned context_size;
+
+ /* The shader userdata register where the 64-bit pointer to the descriptor
+ * array will be stored. */
+ unsigned shader_userdata_reg;
+};
+
+struct si_sampler_views {
+ struct si_descriptors desc;
+ struct pipe_sampler_view *views[NUM_SAMPLER_VIEWS];
+ uint32_t *desc_data[NUM_SAMPLER_VIEWS];
+};
+
+struct si_buffer_resources {
+ struct si_descriptors desc;
+ unsigned num_buffers;
+ enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
+ struct pipe_resource **buffers; /* this has num_buffers elements */
+ uint32_t *desc_storage; /* this has num_buffers*4 elements */
+ uint32_t **desc_data; /* an array of pointers pointing to desc_storage */
+};
+