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nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
[mesa.git]
/
src
/
gallium
/
drivers
/
radeonsi
/
si_state_draw.c
diff --git
a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 7321d1dd3851a512df3ccd490e69695d1df1a7a7..52ecf264ecb55317367daf9dbd836af9a249fdd7 100644
(file)
--- a/
src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/
src/gallium/drivers/radeonsi/si_state_draw.c
@@
-231,9
+231,9
@@
static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_pm4_state *pm4;
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_pm4_state *pm4;
- unsigned i,
exports_ps,
spi_ps_in_control, db_shader_control;
+ unsigned i, spi_ps_in_control, db_shader_control;
unsigned num_sgprs, num_user_sgprs;
unsigned num_sgprs, num_user_sgprs;
- unsigned spi_baryc_cntl = 0, spi_ps_input_ena
, spi_shader_z_format
;
+ unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
uint64_t va;
si_pm4_delete_state(sctx, ps, shader->pm4);
uint64_t va;
si_pm4_delete_state(sctx, ps, shader->pm4);
@@
-243,7
+243,7
@@
static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
return;
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
return;
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
- S_02880C_ALPHA_TO_MASK_DISABLE(sctx->f
b_
cb0_is_integer);
+ S_02880C_ALPHA_TO_MASK_DISABLE(sctx->f
ramebuffer.
cb0_is_integer);
for (i = 0; i < shader->shader.ninput; i++) {
switch (shader->shader.input[i].name) {
for (i = 0; i < shader->shader.ninput; i++) {
switch (shader->shader.input[i].name) {
@@
-264,26
+264,11
@@
static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
}
}
}
}
- for (i = 0; i < shader->shader.noutput; i++) {
- if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
- db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
- if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
- db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
- }
+ db_shader_control |= shader->db_shader_control;
+
if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
db_shader_control |= S_02880C_KILL_ENABLE(1);
if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
db_shader_control |= S_02880C_KILL_ENABLE(1);
- exports_ps = 0;
- for (i = 0; i < shader->shader.noutput; i++) {
- if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
- shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
- exports_ps |= 1;
- }
- if (!exports_ps) {
- /* always at least export 1 component per pixel */
- exports_ps = 2;
- }
-
spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
S_0286D8_BC_OPTIMIZE_DISABLE(1);
spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
S_0286D8_BC_OPTIMIZE_DISABLE(1);
@@
-303,13
+288,7
@@
static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
- if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
- spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
- else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
- spi_shader_z_format = V_028710_SPI_SHADER_32_R;
- else
- spi_shader_z_format = 0;
- si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
+ si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
shader->spi_shader_col_format);
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
shader->spi_shader_col_format);
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
@@
-337,7
+316,7
@@
static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
- shader->cb0_is_integer = sctx->f
b_
cb0_is_integer;
+ shader->cb0_is_integer = sctx->f
ramebuffer.
cb0_is_integer;
shader->sprite_coord_enable = sctx->sprite_coord_enable;
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
shader->sprite_coord_enable = sctx->sprite_coord_enable;
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
@@
-426,15
+405,18
@@
static bool si_update_draw_info_state(struct si_context *sctx,
/* If the WD switch is false, the IA switch must be false too. */
bool ia_switch_on_eop = wd_switch_on_eop;
/* If the WD switch is false, the IA switch must be false too. */
bool ia_switch_on_eop = wd_switch_on_eop;
- si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
+ si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
+ ib->index_size == 4 ? 0xFC000000 : 0xFC00);
+
+ si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
+ si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
+ si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
S_028AA8_PRIMGROUP_SIZE(63) |
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
S_028AA8_PRIMGROUP_SIZE(63) |
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
- si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
- ib->index_size == 4 ? 0xFC000000 : 0xFC00);
-
- si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+ si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
+ si_pm4_cmd_end(pm4, false);
} else {
si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
}
} else {
si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
}
@@
-663,7
+645,7
@@
static void si_update_derived_state(struct si_context *sctx)
si_shader_select(ctx, sctx->ps_shader);
if (!sctx->ps_shader->current->pm4 ||
si_shader_select(ctx, sctx->ps_shader);
if (!sctx->ps_shader->current->pm4 ||
- sctx->ps_shader->current->cb0_is_integer != sctx->f
b_
cb0_is_integer)
+ sctx->ps_shader->current->cb0_is_integer != sctx->f
ramebuffer.
cb0_is_integer)
si_pipe_shader_ps(ctx, sctx->ps_shader->current);
si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
si_pipe_shader_ps(ctx, sctx->ps_shader->current);
si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
@@
-755,14
+737,14
@@
static void si_state_draw(struct si_context *sctx,
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->f
b_
log_samples) |
+ S_028004_SAMPLE_RATE(sctx->f
ramebuffer.
log_samples) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1));
} else {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1));
} else {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->f
b_
log_samples));
+ S_028004_SAMPLE_RATE(sctx->f
ramebuffer.
log_samples));
}
}
}
}
@@
-964,7
+946,7
@@
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* Check flush flags. */
if (sctx->b.flags)
/* Check flush flags. */
if (sctx->b.flags)
- sctx->atoms.cache_flush->dirty = true;
+ sctx->atoms.
s.
cache_flush->dirty = true;
si_need_cs_space(sctx, 0, TRUE);
si_need_cs_space(sctx, 0, TRUE);
@@
-986,20
+968,20
@@
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
#endif
/* Set the depth buffer as dirty. */
#endif
/* Set the depth buffer as dirty. */
- if (sctx->framebuffer.zsbuf) {
- struct pipe_surface *surf = sctx->framebuffer.zsbuf;
+ if (sctx->framebuffer.
state.
zsbuf) {
+ struct pipe_surface *surf = sctx->framebuffer.
state.
zsbuf;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
- if (sctx->f
b_
compressed_cb_mask) {
+ if (sctx->f
ramebuffer.
compressed_cb_mask) {
struct pipe_surface *surf;
struct r600_texture *rtex;
struct pipe_surface *surf;
struct r600_texture *rtex;
- unsigned mask = sctx->f
b_
compressed_cb_mask;
+ unsigned mask = sctx->f
ramebuffer.
compressed_cb_mask;
do {
unsigned i = u_bit_scan(&mask);
do {
unsigned i = u_bit_scan(&mask);
- surf = sctx->framebuffer.cbufs[i];
+ surf = sctx->framebuffer.
state.
cbufs[i];
rtex = (struct r600_texture*)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
rtex = (struct r600_texture*)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;