+ /* Set ring bindings. */
+ if (sctx->esgs_ring) {
+ assert(sctx->chip_class <= GFX8);
+ si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true,
+ true, 4, 64, 0);
+ si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
+ false, 0, 0, 0);
+ }
+ if (sctx->gsvs_ring) {
+ si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false,
+ false, 0, 0, 0);
+ }
+
+ if (sctx->shadowed_regs) {
+ /* These registers will be shadowed, so set them only once. */
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
+
+ assert(sctx->chip_class >= GFX7);
+
+ si_emit_vgt_flush(cs);
+
+ /* Set the GS registers. */
+ if (sctx->esgs_ring) {
+ assert(sctx->chip_class <= GFX8);
+ radeon_set_uconfig_reg(cs, R_030900_VGT_ESGS_RING_SIZE,
+ sctx->esgs_ring->width0 / 256);
+ }
+ if (sctx->gsvs_ring) {
+ radeon_set_uconfig_reg(cs, R_030904_VGT_GSVS_RING_SIZE,
+ sctx->gsvs_ring->width0 / 256);
+ }
+ return true;
+ }
+
+ /* The codepath without register shadowing. */
+ /* Create the "cs_preamble_gs_rings" state. */