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radeonsi: make emit_streamout_output externally accessible
[mesa.git]
/
src
/
gallium
/
drivers
/
radeonsi
/
si_test_dma_perf.c
diff --git
a/src/gallium/drivers/radeonsi/si_test_dma_perf.c
b/src/gallium/drivers/radeonsi/si_test_dma_perf.c
index 657c4ebeff8910f322682525c5f5458c6bcbc026..0a0b9c4a657e85801ceace21c2d4d3fdfded1435 100644
(file)
--- a/
src/gallium/drivers/radeonsi/si_test_dma_perf.c
+++ b/
src/gallium/drivers/radeonsi/si_test_dma_perf.c
@@
-112,11
+112,14
@@
void si_test_dma_perf(struct si_screen *sscreen)
unsigned cs_dwords_per_thread =
test_cs ? cs_dwords_per_thread_list[cs_method % NUM_SHADERS] : 0;
unsigned cs_dwords_per_thread =
test_cs ? cs_dwords_per_thread_list[cs_method % NUM_SHADERS] : 0;
- if (sctx->chip_class == SI) {
- /* SI doesn't support CP DMA operations through L2. */
+ if (test_sdma && !sctx->dma_cs)
+ continue;
+
+ if (sctx->chip_class == GFX6) {
+ /* GFX6 doesn't support CP DMA operations through L2. */
if (test_cp && cache_policy != L2_BYPASS)
continue;
if (test_cp && cache_policy != L2_BYPASS)
continue;
- /* WAVES_PER_SH is in multiples of 16 on
SI
. */
+ /* WAVES_PER_SH is in multiples of 16 on
GFX6
. */
if (test_cs && cs_waves_per_sh % 16 != 0)
continue;
}
if (test_cs && cs_waves_per_sh % 16 != 0)
continue;
}
@@
-151,7
+154,7
@@
void si_test_dma_perf(struct si_screen *sscreen)
unsigned query_type = PIPE_QUERY_TIME_ELAPSED;
if (test_sdma) {
unsigned query_type = PIPE_QUERY_TIME_ELAPSED;
if (test_sdma) {
- if (sctx->chip_class ==
SI
)
+ if (sctx->chip_class ==
GFX6
)
query_type = SI_QUERY_TIME_ELAPSED_SDMA_SI;
else
query_type = SI_QUERY_TIME_ELAPSED_SDMA;
query_type = SI_QUERY_TIME_ELAPSED_SDMA_SI;
else
query_type = SI_QUERY_TIME_ELAPSED_SDMA;
@@
-230,10
+233,11
@@
void si_test_dma_perf(struct si_screen *sscreen)
sctx->cs_user_data[i] = clear_value;
}
sctx->cs_user_data[i] = clear_value;
}
- sctx->flags |= SI_CONTEXT_INV_V
MEM_L1
|
- SI_CONTEXT_INV_S
MEM_L1
;
+ sctx->flags |= SI_CONTEXT_INV_V
CACHE
|
+ SI_CONTEXT_INV_S
CACHE
;
- ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, is_copy ? 2 : 1, sb);
+ ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0,
+ is_copy ? 2 : 1, sb, 0x1);
ctx->bind_compute_state(ctx, cs);
sctx->cs_max_waves_per_sh = cs_waves_per_sh;
ctx->bind_compute_state(ctx, cs);
sctx->cs_max_waves_per_sh = cs_waves_per_sh;
@@
-248,7
+252,7
@@
void si_test_dma_perf(struct si_screen *sscreen)
/* Flush L2, so that we don't just test L2 cache performance. */
if (!test_sdma) {
/* Flush L2, so that we don't just test L2 cache performance. */
if (!test_sdma) {
- sctx->flags |= SI_CONTEXT_W
RITEBACK_GLOBAL
_L2;
+ sctx->flags |= SI_CONTEXT_W
B
_L2;
si_emit_cache_flush(sctx);
}
si_emit_cache_flush(sctx);
}
@@
-345,10
+349,10
@@
void si_test_dma_perf(struct si_screen *sscreen)
if (!r->is_valid)
continue;
if (!r->is_valid)
continue;
- /* Ban CP DMA clears via MC on <=
VI
. They are super slow
+ /* Ban CP DMA clears via MC on <=
GFX8
. They are super slow
* on GTT, which we can get due to BO evictions.
*/
* on GTT, which we can get due to BO evictions.
*/
- if (sctx->chip_class <=
VI
&& placement == 1 &&
+ if (sctx->chip_class <=
GFX8
&& placement == 1 &&
r->is_cp && r->cache_policy == L2_BYPASS)
continue;
r->is_cp && r->cache_policy == L2_BYPASS)
continue;