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DRI2: check for swapAvailable before using swap interval protocol
[mesa.git]
/
src
/
gallium
/
drivers
/
softpipe
/
sp_tile_cache.c
diff --git
a/src/gallium/drivers/softpipe/sp_tile_cache.c
b/src/gallium/drivers/softpipe/sp_tile_cache.c
index 65872cecc4fdfd0fc4ada4af11de0e1b1453808b..aedfdf1b46952cf06fc0919661fe8ffda4d6a4fe 100644
(file)
--- a/
src/gallium/drivers/softpipe/sp_tile_cache.c
+++ b/
src/gallium/drivers/softpipe/sp_tile_cache.c
@@
-32,7
+32,8
@@
* Brian Paul
*/
* Brian Paul
*/
-#include "pipe/p_inlines.h"
+#include "util/u_inlines.h"
+#include "util/u_format.h"
#include "util/u_memory.h"
#include "util/u_tile.h"
#include "sp_tile_cache.h"
#include "util/u_memory.h"
#include "util/u_tile.h"
#include "sp_tile_cache.h"
@@
-161,10
+162,10
@@
sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
PIPE_TRANSFER_READ_WRITE,
0, 0, ps->width, ps->height);
PIPE_TRANSFER_READ_WRITE,
0, 0, ps->width, ps->height);
- tc->depth_stencil = (ps->format == PIPE_FORMAT_S8Z24_UNORM ||
- ps->format == PIPE_FORMAT_X8Z24_UNORM ||
- ps->format == PIPE_FORMAT_Z24S8_UNORM ||
+ tc->depth_stencil = (ps->format == PIPE_FORMAT_Z24S8_UNORM ||
ps->format == PIPE_FORMAT_Z24X8_UNORM ||
ps->format == PIPE_FORMAT_Z24X8_UNORM ||
+ ps->format == PIPE_FORMAT_S8Z24_UNORM ||
+ ps->format == PIPE_FORMAT_X8Z24_UNORM ||
ps->format == PIPE_FORMAT_Z16_UNORM ||
ps->format == PIPE_FORMAT_Z32_UNORM ||
ps->format == PIPE_FORMAT_S8_UNORM);
ps->format == PIPE_FORMAT_Z16_UNORM ||
ps->format == PIPE_FORMAT_Z32_UNORM ||
ps->format == PIPE_FORMAT_S8_UNORM);
@@
-238,7
+239,7
@@
clear_tile(struct softpipe_cached_tile *tile,
{
uint i, j;
{
uint i, j;
- switch (
pf_get_
size(format)) {
+ switch (
util_format_get_block
size(format)) {
case 1:
memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
break;
case 1:
memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
break;
@@
-284,8
+285,9
@@
sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
uint x, y;
uint numCleared = 0;
uint x, y;
uint numCleared = 0;
+ assert(pt->texture);
/* clear the scratch tile to the clear value */
/* clear the scratch tile to the clear value */
- clear_tile(&tc->tile, pt->format, tc->clear_val);
+ clear_tile(&tc->tile, pt->
texture->
format, tc->clear_val);
/* push the tile to all positions marked as clear */
for (y = 0; y < h; y += TILE_SIZE) {
/* push the tile to all positions marked as clear */
for (y = 0; y < h; y += TILE_SIZE) {
@@
-297,13
+299,14
@@
sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
x, y, TILE_SIZE, TILE_SIZE,
tc->tile.data.color32, 0/*STRIDE*/);
x, y, TILE_SIZE, TILE_SIZE,
tc->tile.data.color32, 0/*STRIDE*/);
- /* do this? */
- clear_clear_flag(tc->clear_flags, addr);
-
numCleared++;
}
}
}
numCleared++;
}
}
}
+
+ /* reset all clear flags to zero */
+ memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
+
#if 0
debug_printf("num cleared: %u\n", numCleared);
#endif
#if 0
debug_printf("num cleared: %u\n", numCleared);
#endif
@@
-372,6
+375,7
@@
sp_find_cached_tile(struct softpipe_tile_cache *tc,
if (addr.value != tile->addr.value) {
if (addr.value != tile->addr.value) {
+ assert(pt->texture);
if (tile->addr.bits.invalid == 0) {
/* put dirty tile back in framebuffer */
if (tc->depth_stencil) {
if (tile->addr.bits.invalid == 0) {
/* put dirty tile back in framebuffer */
if (tc->depth_stencil) {
@@
-395,10
+399,10
@@
sp_find_cached_tile(struct softpipe_tile_cache *tc,
if (is_clear_flag_set(tc->clear_flags, addr)) {
/* don't get tile from framebuffer, just clear it */
if (tc->depth_stencil) {
if (is_clear_flag_set(tc->clear_flags, addr)) {
/* don't get tile from framebuffer, just clear it */
if (tc->depth_stencil) {
- clear_tile(tile, pt->format, tc->clear_val);
+ clear_tile(tile, pt->
texture->
format, tc->clear_val);
}
else {
}
else {
- clear_tile_rgba(tile, pt->format, tc->clear_color);
+ clear_tile_rgba(tile, pt->
texture->
format, tc->clear_color);
}
clear_clear_flag(tc->clear_flags, addr);
}
}
clear_clear_flag(tc->clear_flags, addr);
}