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freedreno/ir3: array rework
[mesa.git]
/
src
/
gallium
/
drivers
/
vc4
/
vc4_qpu_defines.h
diff --git
a/src/gallium/drivers/vc4/vc4_qpu_defines.h
b/src/gallium/drivers/vc4/vc4_qpu_defines.h
index b2f028f01945ab0868291b5af59ae8248bd2c678..626dc3be6bed7f5c463e13383bb1547f4d75388e 100644
(file)
--- a/
src/gallium/drivers/vc4/vc4_qpu_defines.h
+++ b/
src/gallium/drivers/vc4/vc4_qpu_defines.h
@@
-147,8
+147,11
@@
enum qpu_mux {
QPU_MUX_A,
QPU_MUX_B,
QPU_MUX_A,
QPU_MUX_B,
- /* non-hardware mux values */
- QPU_MUX_IMM,
+ /**
+ * Non-hardware mux value, stores a small immediate field to be
+ * programmed into raddr_b in the qpu_reg.index.
+ */
+ QPU_MUX_SMALL_IMM,
};
enum qpu_cond {
};
enum qpu_cond {
@@
-197,8
+200,8
@@
enum qpu_pack_a {
enum qpu_unpack {
QPU_UNPACK_NOP,
enum qpu_unpack {
QPU_UNPACK_NOP,
- QPU_UNPACK_16A
_TO_F32
,
- QPU_UNPACK_16B
_TO_F32
,
+ QPU_UNPACK_16A,
+ QPU_UNPACK_16B,
QPU_UNPACK_8D_REP,
QPU_UNPACK_8A,
QPU_UNPACK_8B,
QPU_UNPACK_8D_REP,
QPU_UNPACK_8A,
QPU_UNPACK_8B,
@@
-217,6
+220,9
@@
enum qpu_unpack {
#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
+#define QPU_UPDATE_FIELD(inst, value, field) \
+ (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
+
#define QPU_SIG_SHIFT 60
#define QPU_SIG_MASK QPU_MASK(63, 60)
#define QPU_SIG_SHIFT 60
#define QPU_SIG_MASK QPU_MASK(63, 60)