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radeonsi: reduce type sizes in si_shader_selector
[mesa.git]
/
src
/
gallium
/
drivers
/
vc4
/
vc4_qpu_emit.c
diff --git
a/src/gallium/drivers/vc4/vc4_qpu_emit.c
b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index 47fc0b0928b2ad3dacdded4fc8839b6f37596df5..7926bfd39dad38d0842ed2c61d77567d87ce28ea 100644
(file)
--- a/
src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/
src/gallium/drivers/vc4/vc4_qpu_emit.c
@@
-204,9
+204,9
@@
fixup_raddr_conflict(struct qblock *block,
static void
set_last_dst_pack(struct qblock *block, struct qinst *inst)
{
static void
set_last_dst_pack(struct qblock *block, struct qinst *inst)
{
- bool had_pm = *last_inst(block) & QPU_PM;
- bool had_ws = *last_inst(block) & QPU_WS;
- uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK);
+
ASSERTED
bool had_pm = *last_inst(block) & QPU_PM;
+
ASSERTED
bool had_ws = *last_inst(block) & QPU_WS;
+
ASSERTED
uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK);
if (!inst->dst.pack)
return;
if (!inst->dst.pack)
return;
@@
-226,10
+226,14
@@
static void
handle_r4_qpu_write(struct qblock *block, struct qinst *qinst,
struct qpu_reg dst)
{
handle_r4_qpu_write(struct qblock *block, struct qinst *qinst,
struct qpu_reg dst)
{
- if (dst.mux != QPU_MUX_R4)
+ if (dst.mux != QPU_MUX_R4)
{
queue(block, qpu_a_MOV(dst, qpu_r4()));
queue(block, qpu_a_MOV(dst, qpu_r4()));
- else if (qinst->sf)
- queue(block, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4()));
+ set_last_cond_add(block, qinst->cond);
+ } else {
+ assert(qinst->cond == QPU_COND_ALWAYS);
+ if (qinst->sf)
+ queue(block, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4()));
+ }
}
static void
}
static void
@@
-285,6
+289,8
@@
vc4_generate_code_block(struct vc4_compile *c,
[QOP_MOV] = { QPU_A_OR },
[QOP_FMOV] = { QPU_A_FMAX },
[QOP_MMOV] = { QPU_M_V8MIN },
[QOP_MOV] = { QPU_A_OR },
[QOP_FMOV] = { QPU_A_FMAX },
[QOP_MMOV] = { QPU_M_V8MIN },
+
+ [QOP_MIN_NOIMM] = { QPU_A_MIN },
};
uint64_t unpack = 0;
};
uint64_t unpack = 0;
@@
-413,7
+419,7
@@
vc4_generate_code_block(struct vc4_compile *c,
break;
}
break;
}
- bool handled_qinst_cond = false;
+
ASSERTED
bool handled_qinst_cond = false;
switch (qinst->op) {
case QOP_RCP:
switch (qinst->op) {
case QOP_RCP:
@@
-442,6
+448,7
@@
vc4_generate_code_block(struct vc4_compile *c,
}
handle_r4_qpu_write(block, qinst, dst);
}
handle_r4_qpu_write(block, qinst, dst);
+ handled_qinst_cond = true;
break;
break;
@@
-493,6
+500,7
@@
vc4_generate_code_block(struct vc4_compile *c,
*last_inst(block) = qpu_set_sig(*last_inst(block),
QPU_SIG_COLOR_LOAD);
handle_r4_qpu_write(block, qinst, dst);
*last_inst(block) = qpu_set_sig(*last_inst(block),
QPU_SIG_COLOR_LOAD);
handle_r4_qpu_write(block, qinst, dst);
+ handled_qinst_cond = true;
break;
case QOP_VARY_ADD_C:
break;
case QOP_VARY_ADD_C:
@@
-505,6
+513,7
@@
vc4_generate_code_block(struct vc4_compile *c,
*last_inst(block) = qpu_set_sig(*last_inst(block),
QPU_SIG_LOAD_TMU0);
handle_r4_qpu_write(block, qinst, dst);
*last_inst(block) = qpu_set_sig(*last_inst(block),
QPU_SIG_LOAD_TMU0);
handle_r4_qpu_write(block, qinst, dst);
+ handled_qinst_cond = true;
break;
case QOP_THRSW:
break;
case QOP_THRSW: